ZYNQ PS工程选择 hw_platform0(解决SDK新生成的 hw_platform1)

本文介绍了解决ZYNQPL工程中,因硬件描述文件更新导致的hw_platform版本不匹配问题。通过删除旧工程并重新启动SDK,可以确保工程使用最新的硬件描述文件。

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ZYNQ PL工程更改后 Launch SDK 可能会产生新的 hw_platform,如 hw_platform1,最新的硬件描述文件 hdf 在 hw_platform1 里,而以前创建的工程 Hardware Specification 为 hw_platform0,无法改为 hw_platform1。

解决办法:Launch SDK 后删除 system_wrapper_hw_platform_0 和 system_wrapper_hw_platform_1 工程,删除时勾选 Delete project contents on disk (cannot be undone),然后重新 Launch SDK 即可。

### Zynq PS PCIe Configuration and Driver Setup For configuring the Zynq Processing System (PS) with Peripheral Component Interconnect Express (PCIe), one can utilize Petalinux tools to set up hardware descriptions effectively. The command `petalinux-config --get-hw-description` allows specifying a directory containing an XSA file, which describes the hardware platform including any integrated peripherals like PCIe[^1]. To configure specific settings related to PCIe within the PetaLinux project, modifications might be necessary in files such as those found under directories similar to `sdk/project/cfg/`. For instance, board-specific configurations could reside in makefiles or other configuration scripts that define how different components interact with each other on startup[^2]. When setting up drivers for PCIe functionality, it is important to ensure compatibility between the device tree blob used by Linux running on ARM cores inside Zynq devices and actual hardware connections present on custom boards. This involves editing `.dtsi` files associated with your design to include nodes describing PCI host bridges along with their properties. Here’s an example of what adding support for a generic PCI controller looks like in DTSI format: ```dts pcie@ff980000 { compatible = "xlnx,zynqmp-pcie"; reg = <0xff980000 0x1000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; ``` This snippet defines a node representing a PCI express root complex located at address `0xff980000`, using interrupt line number `73`. Additionally, ensuring proper kernel modules are loaded during boot time may require adjustments to the build system's configuration through menuconfig interfaces provided by PetaLinux Tools. Options relevant to enabling PCIe subsystems should be enabled here so they compile into final images correctly. --related questions-- 1. How does one modify the device tree source (.dts/.dtsi) files specifically for integrating new PCIe endpoints? 2. What steps need to be taken when debugging issues encountered while bringing up PCIe links on Zynq platforms? 3. Can you provide guidance on writing custom initialization routines for handling special cases involving PCIe hotplug events? 4. In terms of performance optimization, what parameters can significantly impact throughput over PCIe buses connected to Zynq SoCs?
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