【HDLBits刷题】Dff8ar..

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

要求创建一个异步清零端的D触发器

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset)begin
        if(areset)
            q <= 8'd0;
        else
            q <= d;
    end
endmodule

这题会有下面这种错误，但是我自己不是很能理解：

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset)begin
        if(!areset)
            q <= d;
        else
            q <= 8'd0;
    end
endmodule

会报错：

cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

这里我只能发表