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数字电路：常见的锁存器浅析

qq_22774445 — Wed, 17 Aug 2022 12:58:27 +0800

由于S-R/S'-R'锁存器在所有时间内对输入都是敏感的，我们期望有一种器件，它只有在使能输入C有效时，才对输入敏感，具有使能端的S-R锁存器(S-R latch with enable)应运而生。总之，作者认为，只要掌握了S-R锁存器，S'-R'锁存器只不过是将输入信号进行反转，我们通过相应的分析即可得出S'-R'锁存器的输出。总结，本次我们介绍了S-R锁存器，S'-R'锁存器，具有使能端的S'-R'锁存器，D锁存器。①S,R均为0，S-R锁存器相当于双稳态元件，通过反馈回路维持电路之前的状态。...

【数电】【verilog】加法器

qq_22774445 — Thu, 11 Aug 2022 22:02:11 +0800

串行全加器是上面这样，但是这种结构的缺点是，必须要等到上一片的结果算出来之后下一片才能进行工作，当级数很高的时候计算的时间将是每一片时间的n倍，会出现组合逻辑延时过长的问题。此时另一种进位方法——超前进位加法器就可以解决这一延时过高的问题。这里实在看不懂可以翻一番数电的超前进位加法器的内容。超前进位加法器就是用电路的复杂度来换时间。3.4位串行加法器（全加器）verilog代码如下：0。1.2输入1bit半加器。2.2输入1bit全加器。4.4位超前进位加法器。...

【HDLBits刷题】Countslow.

qq_22774445 — Tue, 19 Jul 2022 23:13:18 +0800

设计一个0～9的计数器，共10个周期。该计数器采用同步复位且复位为0。但是本题是希望该计数器并不是随着clk的变化而递增，而是随着一个slowena使能信号来控制增加。

【HDLBits刷题】Count1to10.

qq_22774445 — Tue, 19 Jul 2022 22:14:36 +0800

还是1～10的计数器，唯一不同是同步复位为1.

【HDLBits刷题】Count10.

qq_22774445 — Mon, 18 Jul 2022 23:11:10 +0800

代码】【HDLBits刷题】Count10..

【HDLBits刷题】Count15.

qq_22774445 — Mon, 18 Jul 2022 22:38:00 +0800

设计一个4bit的计数器，从0～15，共16个周期。reset是同步复位且复位为0。

【HDLBits刷题】Dualedge..

qq_22774445 — Tue, 12 Jul 2022 22:54:59 +0800

You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and alwa

【HDLBits刷题】Edgecapture..

qq_22774445 — Wed, 06 Jul 2022 20:35:31 +0800

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).Each output bit behaves like a SR flip-flop: The o

【HDLBits刷题】Edgedetect2.

qq_22774445 — Wed, 06 Jul 2022 12:14:28 +0800

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity, in[1] and anyedge[1] are

【HDLBits刷题】Edgedetect.

qq_22774445 — Tue, 05 Jul 2022 12:18:05 +0800

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity,

【HDLBits刷题】Exams/ece241 2013 q7.

qq_22774445 — Mon, 04 Jul 2022 21:33:34 +0800

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge. module top_module ( input clk, input j, input k, output Q

【HDLBits刷题】Exams/ece241 2014 q4.

qq_22774445 — Wed, 27 Apr 2022 18:33:59 +0800

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins. Build this circuit. 开始的时候置0，所以一开始所有的Q都得是0；这个地方放写完之后有个疑惑，就是w1、w2、w3是不是定义成reg类型会更好（reg类型是通过的），但是定义成wire类型也是通过了的： mod

【HDLBits刷题】Exams/2014 q4a.

qq_22774445 — Wed, 27 Apr 2022 12:17:39 +0800

Consider the n-bit shift register circuit shown below: Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers. 1、第一种方法是通过抽象方法，从电路最后面看，写出Q输出： module top_module ( input clk, input w, R

【HDLBits刷题】Exams/m2014 q4d.

qq_22774445 — Mon, 25 Apr 2022 22:51:14 +0800

Implement the following circuit: 图中有一个 D 触发器与一个异或门，触发器的输出 q 和输入信号 in 一起作为异或门的输入。异或门的输入作为触发器的输入 d module top_module ( input clk, input in, output reg out); always @(posedge clk) begin out <= in ^ out; end endmodule .

【HDLBits刷题】Exams/m2014 q4c.

qq_22774445 — Mon, 25 Apr 2022 21:51:38 +0800

Implement the following circuit: 写一个同步复位的D触发器 module top_module ( input clk, input d, input r, // synchronous reset output q); always @(posedge clk)begin if(r) q <= 0; else q <= d; .

【HDLBits刷题】Exams/m2014 q4b.

qq_22774445 — Mon, 25 Apr 2022 12:25:32 +0800

Implement the following circuit: AR 代表 asynchronous reset，所以这是一个带有异步复位的 D 触发器，我们在先前的题目中讨论过异步复位的问题。图中的三角形代表时钟，不再用 CLK 标出。 module top_module ( input clk, input d, input ar, // asynchronous reset output q); always @(posedge c

【数字电路】D锁存器和D触发器的区别

qq_22774445 — Sun, 24 Apr 2022 08:28:33 +0800

我们在数字电路中经常使用到D触发器，有时候还会听到D锁存器这种电路，那么这两种电路到底有什么关系？又存在什么区别？方法一：功能的文字叙述　　1）D锁存器：　　　　功能分析文字描述：C = 0时，输出状态保持不变；C = 1时，输出随输入状态而改变。　　2）D触发器：　　　　功能分析文字描述： CLK=0时，主锁存器工作，接收输入信号Qm = D；从锁存器不工作，输出 Q 保持不变。　　CLK=1时，主锁存器不工作，Qm保持不变；从锁存器工作，将Qm传送到输出端。　

【HDLBits刷题】Exams/m2014 q4a.

qq_22774445 — Sun, 24 Apr 2022 08:00:12 +0800

Implement the following circuit: Note that this is a latch, so a Quartus warning about having inferred a latch is expected. 做一个D触发器 module top_module ( input d, input ena, output q); always @(*)begin if(ena) q = d

【HDLBits刷题】Dff16e..

qq_22774445 — Sat, 23 Apr 2022 23:14:02 +0800

Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[

【HDLBits刷题】Dff8ar..

qq_22774445 — Fri, 22 Apr 2022 19:36:17 +0800

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk. 要求创建一个异步清零端的D触发器 module top_module ( input clk, input areset, // active high asynchronous reset input [7:0] d, output