牛客 VL27 不重叠序列检测

最新推荐文章于 2025-11-24 20:52:15 发布

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/*
非阻塞赋值
data_r <= {data_r[4:0],data}
match  <= (cnt==5) && ({data_r[4:0], data}==6'b011100)

阻塞赋值
data_r  = {data_r[4:0],data}
match  <= (cnt==5) && (data_r==6'b011100)

assign 赋值wire
always块 赋值 reg

*/



`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
    reg [2:0] cnt;
    reg [5:0] data_r;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 0;
        else 
            cnt <= cnt==5? 0: cnt+1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_r <= 6'b0; 
        else
            data_r <= {data_r[4:0], data};
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            match     <= 1'b0;
            not_match <= 1'b0;
        end
        else begin
            match     <= (cnt==5) && ({data_r[4:0], data}==6'b011100);
            not_match <= (cnt==5) && ({data_r[4:0], data}!=6'b011100);
        end
    end
    
endmodule