How to create SVAs in a seperate file

最新推荐文章于 2024-08-16 18:00:44 发布

原创最新推荐文章于 2024-08-16 18:00:44 发布 · 644 阅读

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本文详细介绍如何通过四步创建并应用独立的SystemVerilog断言(SVA)文件：从定义断言到将其绑定到被测模块(DUT)，再到集成进编译流程及最后的调试步骤。

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Following are the steps that create SVAs in a separate file(not mixed in DUT): Step1: create a SVA file, and define all SVAs in that module, : ---------------------------------------------------------------- PktMgrAip.sva --------------------------------------------------------------- module PktMgrAip( //clock and reset clk, reset_n, idle_st, RxToken_st, TxHshk_st, TxData_st, RxData_st, RxHshk_st, RxSof_st, TxPingHshk_st, ); parameter WAITCYCLE=1; //clock and reset input clk; input reset_n; // assertion signals input idle_st; input RxToken_st; input TxHshk_st; input TxData_st; input RxData_st; input RxHshk_st; input RxSof_st; input TxPingHshk_st; property p1; @(posedge clk) $fell(RxToken_st) |-> $rose(RxSof_st|TxData_st|RxData_st); endproperty A1: assert property (p1) ; endmodule Step2: create a bind file, bind the SVA module to the DUT module : ---------------------------------------------------------------- AipBind.sva --------------------------------------------------------------- module AipBind; // bind, DUT_module_instance_name, SVA_module_name, SVA_instance_name bind test_usb_top.pm.PktMgr1 PktMgrAip PktMgrChecker( //clock and reset .clk (clk), .reset_n (reset_n), // assertion signals .idle_st (idle_st), .RxToken_st (RxToken_st), .TxHshk_st (TxHshk_st), .TxData_st (TxData_st), .RxData_st (RxData_st), .RxHshk_st (RxHshk_st), .RxSof_st (RxSof_st), .TxPingHshk_st (TxPingHshk_st), ); endmodule Step3: Add the SVA file+ Bind file into VCS compile file list, then the SVA module will be activated during run-time automatically. Step4: To debug SVAs, invoke DVE, open vpd , and go to the DUT_module_instance hierarchy, you can find the SVA instance there.