定戒慧

huge memory

Q6: Which of the parts in the testbench should add data to the scoreboard? A6: That’s a million dollar question…there are two main approaches and the decision between the two should be done accordin

来自于大牛 Specman Verification  SV is a fact of life and is here to stay. You can feel happy or sad about it, think that it’s a big step to humanity, or a very small step towards standardization, eith

class frame; rand bit valid; constraint user_constraint; constraint user_prob { valid dist { 1:= 90, 0:= 10}; // default distribution // valid dist { 1:=

1.  如何防止在simulation结束仍然还未结束的assertion打印出消息？VCS supports disabling the SVA unfinished message reporting  at the end of simulation, please do as follows:1)      Add VCS compile option  “vcs  -assert

Normally, the interface file  “axi_if.sv “ includes a” AxiPortDefines.inc” file , which has lots of `defines with default values, and may mismatch with your real design.  `define DW_VIP_AXI_ADDR_POR

Below is an example on how to covert the AHB Bus monitor to a Port Monitor for Master: Step 1: in the TBTop, do as below(wire-connection): //***************************************************

Here is a reference of compile script and filelist, the DVE tbug is ok, please have a try.  //---------------------test.files----------------------------------------AxiMaster_rvm.pkgAhbSlave

There is a built-in AXI VIP example that can show you how to generate AXI VIP built-in coverage, it also shows how user can define their own functional coverage groups.You can install the example wi

Results Generaton - Environment or Test Generator?There are a variety of ways to do results checking in a testbench.  They tend to fall into three categories.Tests generate expected results.

/////////////////////////////////////////////////////////////////////////////  /*- unpack2pack(): Convert unpack array to packed.*/  ///////////////////////////////////////////////////////////////

下面给出systemverilog实现的AXI SLAVE VIP 的大致图解

vmm_xactor为我们构建所有的component提供了基类模板。generator，BFM，Driver，Monitor，scoreboard都是从vmm_xactor派生出来的。1. 主要数据成员 vmm_log log; // transactor基类的消息接口 int stream_id; // t

vmm_notify类实现进行通知服务的接口。该通知服务可为并发线程或者事物提供同步机制。1. 通知可以和某一个由vmm_data派生出的status descriptor实例相关联，以便以后重新得到这个关联的status descriptor。如下：this.notify.indicate(int notification_id, vmm_data status);....$

vmm_data的派生类的new函数中，只是用静态的log去初始化消息服务窗口和通知窗口。vmm_data的stream_id和transactor相关，因此stream_id由transactor给出。同理，data_id 由generator在每产生一个产品的时侯increase。function new（）； super.new(log);endfunctionvm

vmm_log 类用于实现消息服务的接口。创建时指定接口名以及实例名。与特定接口名和实例名匹配的所有消息服务接口都受到这种方法的影响。function new（string name， string instance） 在vmm_xactor, vmm_channel, vmm_env这些组件中都有vmm_log这一公共成员，可以说基本所有的基类都有。缺省的是vmm_log在这些基类构

slave从OUT FIFO中拿到data后（阻塞语句），放到总线上，然后等待preadyDelay规定的cycle后将pready有效。pready有效后，可以随机撤销或者保持1的状态。slave从mem中拿到data后，放到总线上，然后等待preadyDelay规定的cycle后将pready有效。pready有效后，可以随机撤销或者保持1的状态。env中提供了访问InBox mail

Slave VIP 简单，只需要一块internal memory就成了，不需要InBox或者OutBox这样的mailbox。只不过，interface有点讲究interface i2c_s_if(inout tri1 sda); // I2C bus signals wire scl; // Tri-state buffer control logic s

如图： 1. readword 每调用一次，最后都会update RdDataPtr，使其自增1.2. 关联数组RdDataArrayBox， Index 是 RdDataPtr， Value 是各个mailbox。 mailbox中放入的是各个transaction。 为何不直接将RdDataArrayBox的值设为各个transaction呢？ 这是个关键所在！不防考虑一下这种

here is block diagram for AXI MASTER VIP.1. semaphore put-then-get can notify all previously queued task are finished.  wait until wait transaction are executed. Just like sync or block instruction.

There are two variables in AXI Slave VIP that control the delay between the AREADY and AVALID: MAX:     dw_vip_axi_port_configuration :: m_nMaxDelay   = 5000 MIN:      m_nAvalidAreadyDelay  = 0;

You can create a “ahbSlaveResponser.sv” that extends from vmm_xactor, and the responses are “transfer” level based, that is, if a burst read/write have 4 transfers, the Slave VIP will send 4 objects t

vmm_test 的实现机制 my_test 通常也称为wrapper class . 上图中红颜色的是静态object

1. 成员解释：stream_id： 指示何种设备发出或传送的transaction。一般和transactor相关data_id： transaction的序号scenario_id：某设备传送的一组transaction，构成了一个scenario.vmm_notify 我们只需要指定一个静态的log就可以构造出一个vmm_data实例。即， new(vmm_log l

对外开放的公共成员： class_name_channel out_chan; //output channelint unsigned stop_after_n_inst; //仅仅生成n个产品，并放入out_chan中class_name randomized_obj; //由blueprint拷贝生成的对象两个事件，GENERATED和DON

1. 定义一个系统级的config类， 如 syscfg.  在类中集中了所有的控制变量（总开关），这些变量决定了是否允许randomize，error injection， delay injection， 产生包的个数，等等     这样可以有效的消除一些不必要的callback。一般callback只是用于将某段代码开放给后面的维护人员以便进行一些复杂的修改之用。     Callb

用过DW VIP的童鞋们一定会感受到里面一堆define文件的痛苦，下面就粗略的谈谈和define相关的知识。1. VIP原代码中大量运用了ifdef ， 即意味着如果外界定义了某宏则使用外界最终定义的宏，否则使用内部预定义的default值。这里支持redefine。2. 外界预定义的宏放在 include/verilog 目录下，主要如下：      AhbMasterDefine

1.  vmm_ms_scenario 也可以利用factory 模式class cpu_rand_scenario extends vmm_ms_scenario; cpu_trans blueprint; `vmm_scenario_new(cpu_rand_scenario) function new()

下面讲一下 vmm_ral_env 中的ral, 以及 vmm_ral_access类的介绍。先看一下vmm_ral_env的源代码：class vmm_ral_env extends `VMM_ENV; vmm_ral_access ral; extern function new(string name = "RAL-Based Verif Env");

在VMM1.1 以及之前，其factory机制的实现是通过以下两种方法实现的1） copy ： 如下class xxx base_transaction factory; .... factory=new(); .... base_transaction tr; $cast(tr, factory.copy())endcl

A better approach is one that was described by Janick in the “Size Does Matter” blog of using `define. Let’s expand on this and see how it works for reusable VIPs. Well, the first thing that comes t

Datastream scoreboard iterators are objects that know how to traverse and navigate theimplementation of the scoreboard. They provide high level methods for moving through thescoreboard and modifyi

RAL model 就是RALF 规定的最高的hierarchy， 一般为sys 或者block。RAL model中定义了field的backdoor和frontdoor操作:peek, poke, read, write.下图展示了RAL的env      synopsys AE recommand that in vmm_rw_xactor, we use

Answer:1. Following is an example of using a parameterized virtual interface with    legal or illegal assignments which works as mentioned(in comments/LRM)    in VCS:------------------

My question is how does it help / add value to have the virtual interface in a wrapper class and initialize / configure using vmm_opts related code ?In summary , how does Interface Wrapper promo

Verification environments need to accommodate changing specifications and at the same time cater to the requirements of different clusters and subsystems.vmm_opts provides the ability to provide a

UVM MAM (Memory Allocation Manager) manages the exclusive allocation of consecutive memory locations called regions. The regions can subsequently be accessed like little memories of their own, witho

VMM application package offers capability to dynamically manage memory shared between multiple clients via Memory Allocation Manager (MAM). MAM helps to simulate HW memory usage patterns and guara

Question:Do I use VMM callbacks or TLM analysis ports to broadcast information from a transactor? Answer:After the OSCI TLM 2.0 features were added to VMM 1.2, it is possible to use anal

如果没有指定timescale，或者 timeunit 那么整个环境会用default的值，（VCS 好像是秒 s）， 如果你在code中使用了......#1ns;......对不起，这一纳秒的delay被完全忽略了。 因为1ns小于timescale的精度, 所以被忽略为零。因此个人以为应该1） 指定timescale2） 尽量用不带单位的delay