FPGA串口通信之Uart发送（基础及应用）

一、Uart 发送模块编写和测试

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`timescale 1ns / 1ps

module uart_tx(
    clk         ,
    rst         ,
    baud_set    ,
    send_go     ,
    data        ,
    uart_tx     ,
    tx_done     
);

input               clk         ;
input               rst         ;
input[2:0]          baud_set    ;
input               send_go     ;
input[7:0]          data        ;
output              uart_tx     ;
output              tx_done     ;

reg                 r_uart_tx     ;
reg                 r_tx_done     ;


reg[17:0]           baud_cnt     ; 
reg[17:0]           baud_counter ;
reg[3:0]            counter1     ;
reg                 bps_clk      ;
reg                 send_en      ;
reg[7:0 ]           r_data       ;

assign              uart_tx    =  r_uart_tx     ;
assign              tx_done    =  r_tx_done     ;

always@(*)begin //波特率选择
    case (baud_set)
        3'd0: baud_cnt <= 1_000_000_000 / 4800 /20    ;
        3'd1: baud_cnt <= 1_000_000_000 / 9600 /20    ;
        3'd2: baud_cnt <= 1_000_000_000 / 14400 /20   ;
        3'd3: baud_cnt <= 1_000_000_000 / 19200 /20   ;
        3'd4: baud_cnt <= 1_000_000_000 / 38400 /20   ;
        3'd5: baud_cnt <= 1_000_000_000 / 56000 /20   ;
        3'd6: baud_cnt <= 1_000_000_000 / 57600 /20   ;
        3'd7: baud_cnt <= 1_000_000_000 / 115200 /20  ;
        default: baud_cnt <= 1_000_000_000 / 4800 /20 ;
    endcase
end
always@(posedge clk,negedge rst)begin
    if(!rst)
        send_en <= 0;
    else if(send_go)
        send_en <= 1;
    else if(tx_done)
        send_en <= 0;
    else
        send_en <= send_en;
end
always@(posedge clk ,negedge rst)begin //波特率计数器，最小计时单位
    if(!rst)
        baud_counter <= 0;
    else if(send_en)begin
        if(baud_counter == baud_cnt - 1)
            baud_counter <= 0;
        else
            baud_counter <= baud_counter + 1;
    end
    else
         baud_counter <= 0;
end
always@(posedge clk ,negedge rst)begin //波特率时钟生成
    if(!rst)
        bps_clk <= 0;
    else if(baud_counter ==  1)
        bps_clk <= 1;
    e