门控时钟检查

最新推荐文章于 2025-07-18 16:50:19 发布

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最新推荐文章于 2025-07-18 16:50:19 发布 · 4.5k 阅读

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门控时钟检查发生在门控信号能控制时钟信号路径的逻辑单元中。检查条件包括：下游时钟必须作为时钟使用，且门控信号不应是时钟或不应作为下游时钟。检查类型分为活动高和活动低，前者发生在与或非门，后者发生在或与非门。报告关注于确保门控信号转换不会在时钟边沿创建活动边缘。

A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. An example is shown in Figure 10-10. The pin of the logic cell connected to the clock is called theclock pin and the pin where the gating signal is connected to is the gating pin. The logic cell where the clock gating occurs is also referred to as thegating cell.

One condition for a clock gating check is that the clock that goes through the cell must be used as a clock downstream. The downstream clock usage can be either as a flip-flop clock or it can fanout to an output port or as a generated clock that refers to the output of the gating cell as its master. If the clock is not used as a clock after the gating cell, then no clock gating check is inferred.

Another condition for the clock gating check applies to the gating signal. The signal at the gating pin of the c