timing verification--Half-Cycle Paths

If a design has both negative-edge triggered flip-flops (active clock edge is falling edge) and positive-edge triggered flip-flops (active clock edge is rising edge), it is likely that half-cycle paths exist in the design. A half-cycle path could be from a rising edge flip-flop to a falling edge flip-flop, or vice versa. Figure 8-19 shows an example when the launch is on the falling edge of the clock of flip-flop UFF5, and the capture is on the rising edge of the clock of flip-flop UFF3.

The hold check always occurs one cycle prior to the capture edge. Since the
capture edge occurs at 12ns, the previous capture edge is at 0ns, and hence
the hold gets checked at 0ns. This effectively adds a half-cycle margin for
hold checking and thus results in a large positive slack on hold.