timing verification---虚假路径

本文探讨了在实际功能操作中,某些定时路径可能不存在或不可行的问题。通过设置假路径,可以忽略这些路径,减少分析空间,使分析仅关注真实路径,从而节省分析时间。然而,过多使用通配符设置假路径可能导致分析变慢。文章提供了设置假路径的建议,并强调了优化假路径使用的最佳实践。

摘要生成于 C知道 ,由 DeepSeek-R1 满血版支持, 前往体验 >

It is possible that certain timing paths are not real (or not possible) in the actual functional operation of the design. Such paths can be turned off during STA by setting these as false paths. A false path is ignored by the STA for analysis.


The advantage of identifying the false paths is that the analysis space is reduced, thereby allowing the analysis to focus only on the real paths. This helps cut down the analysis time as well.However, too many false paths which are wildcarded using the through specification can slow down the analysis.


Few recommendations on setting false paths are given below. To set a false path between two clock domains, use:
set_false_path -from [get_clocks clockA] \
-to [get_clocks clockB]
instead of:
set_false_path -from [get_pins {regA_*}/CP] \
-to [get_pins {regB_*}/D]

The second form is much slower.

Another recommendation is to minimize the usage of -through options, as it adds unnecessary runtime complexity. The -through option should only be used where it is absolutely necessary and there is no alternate way to specify the false path.

From an optimization perspective, another guideline is to not use a false path when a multicycle path is the real intent. If a signal is sampled at a known or predictable time, no matter how far out, a multicycle path specification should be used so that the path has some constraint and gets optimized to meet the multicycle constraint. If a false path is used on a path that is sampled many clock cycles later, optimization of the remaining logic may invariably slow this path even beyond what may be necessary.





评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值