timing verification--Removal Timing Check

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本文介绍了去除定时检查的概念及其重要性。这种检查确保了时钟边沿与异步控制信号释放之间有足够的延迟，使得时钟边沿对信号状态没有影响。文章详细解释了去除时间如何在触发器的异步引脚上定义，并通过实例展示了如何在单元库中指定这些参数。

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A removal timing check ensures that there is adequate time between an active clock edge and the release of an asynchronous control signal. The check ensures that the active clock edge has no effect because the asynchronous control signal remains active until removal time after the active clock edge. In other words, the asynchronous control signal is released (becomes inactive) well after the active clock edge so that the clock edge can have no effect. This is illustrated in Figure 8-20. This check is based on the removal time specified for the asynchronous pin of the flip-flop. Here is an excerpt from the cell library description corresponding to the removal check.

pin(CDN) {
. . .
timing() {
related_pin : "CK";
timing_type : removal_rising;
. . .
}
}

Like a hold check, it is a min path check except that it is on an asynchronous pin of a flip-flop.

The Endpoint shows that it is removal check. It is on the asynchronous pin CDN of flip-flop UFF6. The removal time for this flip-flop is listed as library
removal time with a value of 0.19ns. All asynchronous timing checks are assigned to the async default path group.