timing verification---setup timing check

最新推荐文章于 2024-07-15 17:27:20 发布

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最新推荐文章于 2024-07-15 17:27:20 发布 · 5.1k 阅读

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时序验证中的建立时序检查确保数据在时钟边沿到来之前到达捕获触发器。它通过公式Tlaunch + Tck2q + Tdp < Tcapture + Tcycle - Tsetup进行数学表达，该检查在最慢时钟角进行，使用最长路径。报告中展示了从FF0到FF1的时序路径，包括时钟树延迟和组合逻辑路径延迟。输入和输出时钟边沿、设置和保持检查的差异、时钟源延迟的概念以及如何使用set_input_transition和set_clock_latency命令指定这些参数。此外，还讨论了输入到输出路径的约束和时序分析。

The setup check can be mathematically expressed as:
Tlaunch + Tck2q + Tdp < Tcapture + Tcycle - Tsetup
where Tlaunch is the delay of the clock tree of the launch flip-flop UFF0, Tdp is the delay of the combinational logic data path and Tcycle is the clock period.
Tcapture is the delay of the clock tree for the capture flip-flop UFF1.

Since the setup check poses a max constraint, the setup check always uses the longest or the max timing path. For the same reason, this check is normally
verified at the slow corner where the delays are the largest.

1.Flip-flop to Flip-flop Path

The Path Type line indicates that the delays shown in this report are all max path delays indicating that this is a setup check. This is because
setup checks correspond to the max (or longest path) delays through the logic. Note that the hold checks correspond to the min (or shortest path)
delays through the logic.

The launch path takes 0.26ns to get to the D pin of flip-flop UFF1 - this is the arrival time at the input of the capture flip-flop. The capture edge
(which is one cycle away since this is a setup check) is at 10ns. A clock uncertainty of 0.3ns was specified for this clock - thus, the clock period is reduced
by the uncertainty margin. The clock uncertainty includes the variation in cycle time due to jitter in the clock source and any other timing
margin used for analysis.The setup time of the flip-flop 0.04ns (called library setup time), is deducted from the total capture path yielding a required

time of 9.66ns.

What is the clock network delay in the timing report and why is it marked as ideal? This line in the timing report indicates that the clock trees are treated
as ideal, that any buffers in the clock path are assumed to have zero delay. Once the clock trees are built, the clock network can be marked as propagated

- which causes the clock paths to show up with real delays, as shown in the next example timing report. The 0.11ns delay is the clock network delay on the launch

clock and the 0.12ns delay is the clock network delay on the capture flip-flop.