Tessent Multi-Die简介

Introduction to Tessent Multi-Die

With the latest developments in electronic industry to support revolutionary complex systems such as Autonomous vehicles or AI products/chips system-in-package becomes inevitable. System-in-package, SiP  which is “more-than-Moore’s law”, incorporates multiple dies inside one package making heterogenous integration possible. In a SiP, each die connects to other dies using either 2.5D or 3D interconnect technology. 

While in 2.5D ICs chiplets are integrated on an interposer layer horizontally, in 3D ICs the chiplets are stacked vertically. Tessent provides design steps to insert test logic for each die, mechanism to access individual die, to perform die-die interconnect test and so on.

In 2.5D IC, we insert DFT logic in the dies, make the whole package compliant with IEEE 1149.