【RISC-V设计-11】- RISC-V处理器设计K0A之TOP
文章目录
1.简介
本文是对前几篇文章设计的模块的例化,作为RISCV-K0A
的设计顶层,着重于架构和框架的搭建,并未深入涉及具体的逻辑功能层面。
2.顶层设计
3.端口说明
序号 | 端口 | 位宽 | 方向 | 说明 |
---|---|---|---|---|
1 | core_clk | 1 | input | 内核时钟 |
2 | core_rstn | 1 | input | 内核复位信号,低有效 |
3 | bus_avalid | 1 | output | 总线的地址有效信号 |
4 | bus_aready | 1 | input | 总线的地址就绪信号 |
5 | bus_write | 1 | output | 总线的写使能信号 |
6 | bus_addr | 18 | output | 总线地址 |
7 | bus_strb | 4 | output | 总线写字节有效信号 |
8 | bus_wdata | 32 | output | 总线写数据 |
9 | bus_rvalid | 1 | input | 总线读有效信号 |
10 | bus_rready | 1 | output | 总线读就绪信号 |
11 | bus_rdata | 32 | input | 总线读数据 |
12 | irq_lines | 16 | input | 外部中断信号,高电平/脉冲触发 |
4.代码设计
// -------------------------------------------------------------------------------------------------
// Copyright 2024 Kearn Chen, kearn.chen@aliyun.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// -------------------------------------------------------------------------------------------------
// Description :
// 1. Core Top Wrapper
// -------------------------------------------------------------------------------------------------
module k0a_core_top (
input wire core_clk