【RISC-V设计-12】- RISC-V处理器设计K0A之验证环境

【RISC-V设计-12】- RISC-V处理器设计K0A之验证环境

1.简介

在前几篇文章中，分别介绍了各个模块的设计，本篇文章将会针对k0a_core_top层搭建一个简单的验证环境。

2.验证顶层

3.顶层代码

// -------------------------------------------------------------------------------------------------
// Copyright 2024 Kearn Chen, kearn.chen@aliyun.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// 
//     http://www.apache.org/licenses/LICENSE-2.0
// 
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// -------------------------------------------------------------------------------------------------
// Description :
//             1. testbench for simulation
// -------------------------------------------------------------------------------------------------

`timescale 1ns/10ps

module test_top();

reg          core_clk    ;
reg          core_rstn   ;

wire         bus_avalid  ;
wire         bus_aready  ;
wire         bus_write   ;
wire [17:0]  bus_addr    ;
wire [3:0]   bus_strb    ;
wire [31:0]  bus_wdata   ;
wire         bus_rvalid  ;
wire         bus_rready  ;
wire [31:0]  bus_rdata   ;

reg  [15:0]  irq_lines   ;

k0a_core_top dut (
    .core_clk       (core_clk       ),
    .core_rstn      (core_rstn      ),
    .bus_avalid     (bus_avalid     ),
    .bus_aready     (bus_aready     ),
    .bus_write      (bus_write      ),
    .bus_addr       (bus_addr       ),
    .bus_strb       (bus_strb       ),
    .bus_wdata      (bus_wdata      ),
    .bus_rvalid     (bus_rvalid     ),
    .bus_rready     (bus_rready     ),
    .bus_rdata      (bus_rdata      ),
    .irq_lines      (irq_lines      )
);

slave_model u_slave (
    .clk            (core_clk       ),
    .rstn           (core_rstn      ),
    .avalid         (bus_avalid     ),
    .aready         (bus_aready     ),
    .write          (bus_write      ),
    .addr           (bus_addr