FPGA学习日记（18）--数码管动态显示

 

数据生成模块

 

module data_gen
#(
   parameter CNT_MAX = 23'd4999_999 ,
   parameter DATA_MAX = 20'd999_999 
)
(   
    input    wire         sys_clk     ,
    input    wire         sys_rst_n   ,
           
    output   reg   [19:0] data        ,
    output   wire  [5:0]  point       ,
    output   wire         sign        ,
    output   reg          seg_en      
    
);

reg [22:0] cnt_100ms;
reg cnt_flag ;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        cnt_100ms <= 23'd0;
    else if(cnt_100ms == CNT_MAX)
        cnt_100ms <= 23'd0;
    else
        cnt_100ms <= 1'b1 + cnt_100ms;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        cnt_flag <= 1'b0;
    else if (cnt_100ms == CNT_MAX - 1)
        cnt_flag <= 1'b1;
    else 
        cnt_flag <= 1'b0;    
        
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        data <= 20'd0;
    else if((data == DATA_MAX)&&(cnt_flag == 1'b1))
        data <= 20'd0;
    else if(cnt_flag == 1'b1)
        data <= data + 1'b1;
    else 
        data <= data;

assign point = 6'b000_000;
assign sign  = 1'b0;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        seg_en <= 1'b0;
    else 
        seg_en <= 1'b1;

endmodule         

`timescale 1ns/1ns
module tb_data_gen();

reg   sys_clk     ;
reg   sys_rst_n   ;
                    
wire [19:0] data   ;
wire [5:0]  point  ;
wire        sign   ; 
wire        seg_en ;


initial 
    begin 
        sys_clk =1'b1;
        sys_rst_n <= 1'b0;
        #20 
        sys_rst_n <= 1'b1;
    end
 
always #10 sys_clk = ~sys_clk;

data_gen
#(
  .CNT_MAX (9)   ,
  .DATA_MAX(9)   
)
data_gen_inst
(
   .sys_clk   (sys_clk  ) , 
   .sys_rst_n (sys_rst_n) ,
   .data  (data  ),
   .point (point ),
   .sign  (sign  ),
   .seg_en(seg_en)

);
endmodule

计数器 cnt_flag

data

加入BCD码模块

  

 

module bcd_8421
(
    input       sys_clk     ,
    input       sys_rst_n   ,
    input wire [19:0] data  ,
                        
    output reg [3:0] unit  ,
    output reg [3:0] ten   ,
    output reg [3:0] hun   , 
    output reg [3:0] tho   ,
    output re