package pack1;
import uvm_pkg::*;
`include "uvm_macros.svh"
class obj1 extends uvm_object;
bit [7:0] data0 = 'haa;
bit [7:0] data1 = 'hbb;
`uvm_object_utils(obj1)
function new();
super.new();
`uvm_info("class:obj1",$sformatf("data0:%x!",data0),UVM_LOW)
`uvm_info("class:obj1",$sformatf("data1:%x!",data1),UVM_LOW)
endfunction
extern task xxx();
endclass
task obj1::xxx();
`uvm_info("class:obj1",$sformatf("this is xxx task"),UVM_LOW)
endtask
class obj2 extends obj1;
bit [7:0] data1 = 'hcc;
`uvm_object_utils(obj2)
function new();
`uvm_info("class:obj2",$sformatf("data1:%x!",data1),UVM_LOW)
`uvm_info("class:obj2",$sformatf("super.data1:%x!",super.data1),UVM_LOW)
`uvm_info("class:obj2",$sformatf("this.data1:%x!",this.data1),UVM_LOW)
endfunction
endclass
class comp1 extends uvm_component;
`uvm_component_utils(comp1)
function new(string name = "comp1",uvm_component parent = null);
super.new(name,parent);
`uvm_info("class:comp1",$sformatf("handle is %s",name), UVM_LOW)
endfunction
endclass
class comp2 extends comp1;
`uvm_component_utils(comp2)
function new(string name = "comp2", uvm_component parent = null);
super.new(name, parent);
`uvm_info("class:comp2",$sformatf("handle is %s",name), UVM_LOW)
endfunction
endclass
class test1 extends uvm_test;
comp2 a,b,c;
`uvm_component_utils(test1)
function new(string name = "test1", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("test1",$sformatf("build"), UVM_LOW)
a = new("a",null);
b = new("b",this);
c = comp2::type_id::create("c",null);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info("test1",$sformatf("run0"), UVM_LOW)
#1us;
`uvm_info("test1",$sformatf("run1"), UVM_LOW)
phase.drop_objection(this);
endtask
endclass
class a extends uvm_component;
bit [3:0] va ='ha;
`uvm_component_utils(a)
function new(string name = "a", uvm_component parent = null);
super.new(name, parent);
endfunction
endclass
class b extends a;
`uvm_component_utils(b)
function new(string name = "b", uvm_component parent = null);
super.new(name, parent);
super.va = 'hb;
endfunction
endclass
class x extends uvm_test;
a handle0,handle1;
`uvm_component_utils(x)
function new(string name = "x", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
handle0 = a::type_id::create("handle0",this);
handle1 = a::type_id::create("handle1",this);
`uvm_info("x build phase",$sformatf("handle0.va=%x",handle0.va), UVM_LOW)
`uvm_info("x build phase",$sformatf("handle1.va=%x",handle1.va), UVM_LOW)
endfunction
endclass
class y extends x;
`uvm_component_utils(y)
function new(string name = "y", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
set_type_override("a", "b");
super.build_phase(phase);
endfunction
endclass
endpackage
module hardware1;
import pack1::*;
import uvm_pkg::*;
initial begin
obj2 handle0;
obj1 handle1;
handle0 = new();
handle1 = new();
handle1.xxx();
run_test("y");
end
endmodule
interface interf1;
logic [31:0] addr;
logic [31:0] data;
endinterface
package pack2;
import uvm_pkg::*;
`include "uvm_macros.svh"
class comp2 extends uvm_component;
virtual interf1 vif;
`uvm_component_utils(comp2)
function new(string name = "comp2", uvm_component parent = null);
super.new(name, parent);
`uvm_info("CREATE", $sformatf("unit type [%s] created", name), UVM_LOW)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual interf1)::get(this, "", "label0", vif))begin
`uvm_error("config_db", "can't find label0 in this hierarchy!")
end
else begin
`uvm_info("config_db","config_success!", UVM_LOW)
end
endfunction
endclass
class comp1 extends uvm_component;
int value;
`uvm_component_utils(comp1)
function new(string name = "comp1", uvm_component parent = null);
super.new(name, parent);
`uvm_info("CREATE", $sformatf("unit type [%s] created", name), UVM_LOW)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(int)::get(this, "", "val", value))begin
`uvm_error("config_db", "can't find val in this hierarchy!")
end
else begin
`uvm_info("config_db","config_success!", UVM_LOW)
`uvm_info("config_db", $sformatf("Value is %h!", value), UVM_LOW)
end
endfunction
endclass
class obj1 extends uvm_object;
bit [7:0] data0 = 'haa;
`uvm_object_utils(obj1)
function new();
super.new();
endfunction
endclass
class comp0 extends uvm_component;
obj1 o1;
`uvm_component_utils(comp0)
function new(string name = "comp0", uvm_component parent = null);
super.new(name, parent);
`uvm_info("CREATE", $sformatf("unit type [%s] created", name), UVM_LOW)
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(obj1)::get(this, "", "object", o1))begin
`uvm_error("config_db", "can't find object in this hierarchy!")
end
else begin
`uvm_info("config_db","config_success!", UVM_LOW)
`uvm_info("config_db", $sformatf("o1.data0 is %h!", o1.data0), UVM_LOW)
end
endfunction
endclass
class uvm_config_test extends uvm_test;
comp2 c2;
comp1 c1;
comp0 c0;
obj1 o;
`uvm_component_utils(uvm_config_test)
function new(string name = "uvm_config_test", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
c2 = comp2::type_id::create("c2",this);
uvm_config_db#(int)::set
(uvm_root::get(), "uvm_test_top.*", "val", 'ha5a5_5a5a);
c1 = comp1::type_id::create("c1",this);
o = obj1::type_id::create();
o.data0 = 8'haa;
uvm_config_db#(obj1)::set
(uvm_root::get(), "uvm_test_top.*", "object",o);
c0 = comp0::type_id::create("c0",this);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
#1us;
phase.drop_objection(this);
endtask
endclass
endpackage
module hardware2;
import pack2::*;
import uvm_pkg::*;
interf1 if0();
initial begin
uvm_config_db#(virtual interf1)::set
(uvm_root::get(), "uvm_test_top.*", "label0", if0);
run_test("uvm_config_test");
end
endmodule