嵌入式 - MLX81322存储器介绍

原创

于 2025-02-08 10:40:10 发布 · 831 阅读

7 ·

CC 4.0 BY-SA版权

文章标签：

#笔记

13.3.3. Memories

13.3.3.1. Flash memory

The 32k byte flash memory is organized in 256 pages of 16 x 72bit (64 user bits per 72bit).

The 64 user bits are secured by a hardware ECC mechanism (ECC = Error Checking and Correcting) and additional 8 bits. By this the memory can correct single bit fail per quad word, and detect double bit fail per quad word. The double bit error will be signalized via the signal FL_DATA_CORRUPTED in port EEPROM_FLASH (see section 13.3.3.1.1).

The MLX16 doesn't check if there was a double bit failure. The customer should do a CRC check or maybe get a critical interrupt because of an invalid opcode due to the possibility of a corrupted Flash content. The SW should react accordingly and should drive the system in a secure mode.

The write of a flash memory page takes typically 5ms the erase procedure typically 30ms. The memory is read by the CPU at fu