主控
主控基于是FPGA或CPLD,CPLD价格更低
主要功能:
(1)程序支持64阀
(2)串口按照协议接收数据,并驱动阀,
(3)驱动指示灯
引脚配置如下:
set_property DRIVE 12 [get_ports {lvds_t[1]}]
set_property DRIVE 12 [get_ports {lvds_t[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports SW3]
set_property IOSTANDARD LVCMOS33 [get_ports SW2]
set_property IOSTANDARD LVCMOS33 [get_ports SW1]
set_property IOSTANDARD LVCMOS33 [get_ports SW0]
set_property PULLDOWN true [get_ports SW0]
set_property PULLDOWN true [get_ports SW1]
set_property PULLDOWN true [get_ports SW2]
set_property PULLDOWN true