Dualedge

您熟悉在时钟的正边缘或负边缘触发的。在时钟的两个边沿触发双边沿触发触发器。但是，FPGA 没有双边触发触发器，并且始终不接受 @（posedge clk 或 negedge clk） 作为敏感度列表。

 You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

也就是说，对输入的信号延时半个时钟周期

 

 

module top_module (
    input clk,
    input d,
    output q
);
    wire clk_reg;
    reg d1;
    reg d2;
    /*
    assign q = clk? d1 : d2;
    always@ (posedge clk ) begin
          d1 <= d;
    end
    
    always@ (negedge clk ) begin
          d2 <= d;
    end
    */
    
     // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
     assign q = d1 ^ d2;
     always@ (posedge clk ) begin
          d1 <= d ^ d2;
    end
    
    always@ (negedge clk ) begin
          d2 <= d ^ d1;
    end
    
endmodule

参考 ：HDLBits学习笔记—— Dualedge_鸢尾__的博客-优快云博客