Exams/m2014 q4c

Implement the following circuit:

 同步复位

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);

    always@ (posedge clk)
        if(r == 1)
            q <= 1'b0;
    	else 
            q <= d;
endmodule