Verilog学习笔记HDLBits——Finite State Machines(1)

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前言

有限状态机

一、Finite State Machines

1.Simple FSM 1(asychronous reset)

Practice:This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1s, but using asynchronous reset.
翻译:实现下面这个2状态、1输入、1输出的摩尔型状态机（异步复位、复位状态为B）。

提示：
状态机的实现首推三段式状态机，可能一开始觉得三段式状态机写起来太麻烦，但是相信我当你的状态机越来越复杂的时候，三段式状态机一定是写起来最简单的那种。
Solution（不唯一，仅供参考）：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state;			//定义现抬寄存器
    reg next_state;		 //定义次态寄存器
	//三段式状态机第一段：同步时序描述状态转移
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)begin
            state<=B;
        end
        else begin
            state<=next_state;
        end
    end
    //三段式状态机第二段：组合逻辑判断状态转移条件，描述转移规律以及输出
    always @(*) begin    // This is a combinational always block
        if(areset)begin
            next_state=B;
        end
        else begin
            case(state)
                A:begin
                    if(!in) next_state=B;
                    else    next_state=A;
                end
                B:begin
                    if(!in) next_state=A;
                    else 	next_state=B;
                end
                default:;
            endcase
        end
    end

	//三段式状态机第三段：时序逻辑描述输出
	always @(posedge clk or posedge areset) begin
        if(areset)begin
           out<=1'b1; 
        end
        else begin
            case(next_state)
                A: out<=0;
                B: out<=1;
                default: out<=1;
            endcase
        end
    end
endmodule

Timing Diagram

2.Simple FSM 1(synchronous reset)

Practice：This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1, but using synchronous reset.
翻译： 实现下面这个2状态、1输入、1输出的摩尔型状态机（同步复位、复位状态为B）。

Solution（不唯一，仅供参考）：

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;
	
	parameter A=2'b01;
    parameter B=2'b00;
    reg [1:0] cur_state, next_state;
	//第一段
    always @(posedge clk) begin
        if (reset) begin  
            cur_state<=B;
        end
		else begin
           cur_state<=next_state; 
        end
    end
    //第二段
    always @(*)begin
        if(reset)begin
            next_state=B;
        end
        else begin
            case(cur_state)
                A:begin
                    if(!in) next_state=B;
                    else  	next_state=A;
                end
                B:begin
                    if(!in) next_state=A;
                    else   	next_state=B;
                end
                default:;
            endcase
        end     
    end
    //第三段
    always @(posedge clk)begin
        if(reset)begin
            out<=1;
        end
        else begin
            case(next_state)
                A: out<=0;
                B: out<=1;
                default: out<=1;
            endcase
        end
    end

endmodule

Timing Diagram

3.Simple FSM 2(asynchronous reset)

Practice：Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
翻译：
实现下面这个2状态、2输入、1输出的摩尔型状态机（异步复位、复位状态为B）。

Solution（不唯一，仅供参考）：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg [1:0] cur_state, next_state;
	
    always @(posedge clk or posedge areset)begin
        if(areset)begin
           cur_state<=OFF; 
        end
        else begin
           cur_state<=next_state;
        end
    end
    always @(*) begin
        if(areset)begin
           next_state=OFF;
        end
        else begin
            case(cur_state)
               OFF:begin
                   if(j) next_state=ON;
                   else  next_state=OFF;
               end
                ON:begin
                    if(k) next_state=OFF;
                    else  next_state=ON;
                end
                default:;
            endcase
        end
    end

    always @(posedge clk or posedge areset) begin
        if(areset)begin
           out<=0; 
        end
        else begin
            case(next_state)
                OFF: out<=0;
                ON:  out<=1;
                default: out<=0;
            endcase
        end
    end

endmodule

Timing Diagram

4.Simple FSM 2(synchronous reset)

Practice：Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
翻译：
实现下面这个2状态、2输入、1输出的摩尔型状态机（同步复位、复位状态为B）。

Solution（不唯一，仅供参考）：

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg cur_state, next_state;
	//第一段
    always @(posedge clk) begin
        if(reset)begin
           cur_state<=OFF; 
        end
        else begin
           cur_state<=next_state;
        end
    end
    //第二段
    always @(*) begin
        if(reset)begin
           next_state=OFF; 
        end
        else begin
            case(cur_state)
                OFF:begin
                    if(j) next_state=ON;
                    else  next_state=OFF;
                end
                ON:begin
                    if(k) next_state=OFF;
                    else  next_state=ON;
                end
                default:;
            endcase
        end
    end
	//第三段
    always @(posedge clk) begin
        if(reset)begin
           out<=0; 
        end
        else begin
            case(next_state)
                OFF: out<=0;
                ON:  out<=1;
                default:;
            endcase
        end
    end


endmodule

Timing Diagram

5.Simple state transition 3

Practice：Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table.
翻译： 下面是具有一个输入、一个输出和四个状态的摩尔状态机的状态转移表。使用以下状态编码:A=2’b00, B=2’b01, C=2’b10, D=2’b11。

仅实现此状态机的状态转换逻辑和输出逻辑(组合逻辑部分)。给定当前状态(state)，根据状态转换表计算next_state和输出(out)。

提示：
这里使用2段式的状态机就行（题目要求），一段实现状态转移；另一端实现输出。
Solution（不唯一，仅供参考）：

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //
	//状态机第一段：描述状态转移
    parameter A=2'b00, B=2'b01, C=2'b10, D=2'b11;
    always @(*)begin
        case(state)
            A:begin
                if(in) next_state=B;
                else   next_state=A;
            end
            B:begin
                if(in) next_state=B;
                else   next_state=C;
            end
            C:begin
                if(in) next_state=D;
                else   next_state=A;
            end
            D:begin
                if(in) next_state=B;
                else   next_state=C;
            end
            default:;
        endcase
    end
    //状态机第二段：组合逻辑实现输出  
    always @(*)begin
        case(state)
            A: out=0;
            B: out=0;
            C: out=0;
            D: out=1;
            default:;
        endcase
    end
endmodule

6.Simple one-hot state transition 3

Practice：The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.

Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you’re not trying to do something more complicated).
翻译： 实现下面的摩尔状态机，下表是状态转移图，1输入1输出4状态。使用如下的独热码编码方式：A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000。
这个状态机只实现状态跳转逻辑和输出逻辑。已经给出了现态state，根据状态转移图计算出次态和输出。

提示
基本和上题一致，只是编码方式要求改成独热码方式。独热码是使用一位有效的编码方式，这意味着使用独热码编码，有几个状态，那么编码寄存器的位宽就有几位。这无疑多消耗了寄存器资源。
独热码：和格雷码相比，虽然独热码多用了触发器，但所用组合电路可以省一些（相当于进行了一次译码操作），因而使电路的速度和可靠性有显著提高，而总的单元数并无显著增加。因为独热码只有一位的变化，所以更适用于高速系统。

Solution（不唯一，仅供参考）：

module top_module(
    input in,
    input [3:0