Verilog学习笔记HDLBits——Counters

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前言

一、Counters

1. Four-bit binary counter

Practice:Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
翻译:构建一个4位二进制计数器，从0到15(包括15)，周期为16。复位输入是同步的，应该将计数器复位为0。

Solution（不唯一，仅供参考）：

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output reg [3:0] q);
    always @(posedge clk)begin
        if(reset)begin
           q<=0; 
        end
        else begin
            if(q==4'b1111)begin
                q<=0;
            end
            else begin
               q<=q+1; 
            end
        end
    end
endmodule

Timing Diagram

2. Decade counter

Practice：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.
翻译：同样是 4bit 计数器，本题只计数到 0～9，周期（period）为 10，同步复位且复位为 0。时序图如下：

Solution（不唯一，仅供参考）：

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output reg [3:0] q);
 	always @(posedge clk)begin
        if(reset)begin
           q<=0; 
        end
        else begin
            if(q==4'b1001)begin
                q<=0;
            end
            else begin
               q<=q+1; 
            end
        end
    end
endmodule

Timing Diagram

3. Decade counter again

Practice：Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
翻译：本题与上题类似，只需计数1-10，复位到1.

Solution（不唯一，仅供参考）：

module top_module (
    input clk,
    input reset,
    output reg [3:0] q);
    always @(posedge clk)begin
        if(reset)begin
           q<=1;
        end
        else begin
            if(q==4'b1010)begin
               q<=1; 
            end
            else begin
               q<=q+1;
            end
        end
    end
endmodule

Timing Diagram

4. Slow decade counter

Practice：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

翻译：设计一个 0～9 的计数器，共 10 个周期。该计数器采用同步复位且复位为 0。但是本题是希望该计数器并不是随着 clk 的变化而递增，而是随着一个 slowena 使能信号来控制增加。时序图如下图所示：

Solution（不唯一，仅供参考）：

module top_module (
    input clk,
    input slowena,
    input reset,
    output reg [3:0] q);
    always @(posedge clk)begin
        if(reset)begin
           q<=0; 
        end
        else if(slowena)begin
            if(q==4'b1001)begin
            	q<=0;
            end
       		else begin
            	q<=q+1;
            end
        end
    	else begin
           q<=q; 
        end
    end
endmodule

Timing Diagram

5. Counter 1-12

Practice：Design a 1-12 counter with the following inputs and outputs:
Reset: Synchronous active-high reset that forces the counter to 1
Enable:Set high for the counter to run
Clk :Positive edge-triggered clock input
Q[3:0] :The output of the counter
c_enable, c_load, c_d[3:0] :Control signals going to the provided 4-bit counter, so correct operation can be verified.
翻