Verilog学习笔记HDLBits——Finding bugs in code

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前言

一、Finding bugs in code

1.Mux

Practice:This 8-bit wide 2-to-1 multiplexer doesn’t work. Fix the bug(s).
翻译:
这个8位宽的2对1多路复用器不能工作。修复bug

Solution（不唯一，仅供参考）：

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out = sel?a:b;

endmodule

Timing Diagram

2.NAND

Practice：This three-input NAND gate doesn’t work. Fix the bug(s).
You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e );

翻译：这个三输入与非门不能工作。修复bug

Solution（不唯一，仅供参考）：

module top_module (input a, input b, input c, output out);//

    wire nout;
    andgate inst1 ( nout, a, b, c, 1, 1 );
	assign out=~nout;
    
endmodule

Timing Diagram

3.Mux

Practice：
This 4-to-1 multiplexer doesn’t work. Fix the bug(s).

You are provided with a bug-free 2-to-1 multiplexer:

module mux2 (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out
);

翻译：
这个4对1的多路复用器不能工作。修复bug

Solution（不唯一，仅供参考）：

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux0, mux1;
    mux2 mux00 ( sel[0],    a,    b, mux0 );
    mux2 mux10 ( sel[0],    c,    d, mux1 );
    mux2 mux20 ( sel[1], mux0, mux1,  out );

endmodule

Timing Diagram

4.Add/sub

Practice：The following adder-subtractor with zero flag doesn’t work. Fix the bug(s).
翻译：下面的加-减法零标志无效。修复bug

Solution（不唯一，仅供参考）：

module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
            default:;
        endcase

        if (!out)
            result_is_zero = 1;
		else 
        	result_is_zero=0;
    end
endmodule

Timing Diagram

5.Case statement

Practice：
This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).

翻译：这个组合电路应该可以识别8位键盘扫描码的0到9按键。它应该指示10个分支中是否有一个被识别(有效)，如果是，那么哪个按键被检测到。请修复bug。

Solution（不唯一，仅供参考）：

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid );//

     always @(*)
        case (code)
            8'h45: begin
                out = 0;
                valid = 1;
            end
            8'h16: begin
                out = 1;
                valid = 1;
            end
            8'h1e: begin
                out = 2;
                valid = 1;
            end
            8'h26: begin
                out = 3;
                valid = 1;
            end
            8'h25: begin
                out = 4;
                valid = 1;
            end
            8'h2e: begin
                out = 5;
                valid = 1;
            end
            8'h36: begin
                out = 6;
                valid = 1;
            end
            8'h3d: begin
                out = 7;
                valid = 1;
            end
            8'h3e: begin
                out = 8;
                valid = 1;
            end
            8'h46: begin
                out = 9;
                valid = 1;
            end
            default: begin
                out = 0;
                valid = 0;
            end
        endcase

endmodule

Timing Diagram

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