Dff8ar 习题笔记

最新推荐文章于 2025-07-14 21:37:47 发布

原创最新推荐文章于 2025-07-14 21:37:47 发布 · 288 阅读

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该模块描述了一个使用Verilog编写的8位D触发器阵列，每个触发器都具有活动高异步复位功能。在时钟的正沿触发时，如果复位信号为高，则触发器的输出被清零；否则，输出跟随输入数据d变化。敏感列表中包含posedgeclk和posedgereset，即使reset是电平触发，这样设计也能确保在复位信号变为高时有效复位。

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

module top_module(
    input clk,
    input [7:0] d,
    input areset,
    output reg [7:0] q);
    
    // The only difference in code compared to synchronous reset is in the sensitivity list.
    always @(posedge clk, posedge areset)
        if (areset)
            q <= 0;
        else
            q <= d;


    // In Verilog, the sensitivity list looks strange. The FF's reset is sensitive to the
    // *level* of areset, so why does using "posedge areset" work?
    // To see why it works, consider the truth table for all events that change the input 
    // signals, assuming clk and areset do not switch at precisely the same time:
    
    //  clk        areset        output
    //   x         0->1        q <= 0; (because areset = 1)
    //   x         1->0        no change (always block not triggered)
    //  0->1       0        q <= d; (not resetting)
    //  0->1       1        q <= 0; (still resetting, q was 0 before too)
    //  1->0       x        no change (always block not triggered)
    
endmodule