【System Verilog and UVM基础入门27】UVM Virtual Sequence

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已于 2024-05-31 17:46:21 修改

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于 2022-03-14 14:27:18 首次发布

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UVM Virtual Sequence是用于在环境中不同sequencers上启动多个序列的容器。它通常由虚拟sequencer执行，该sequencer拥有对真实sequencers的句柄。当需要在不同环境中运行不同的序列时，就需要使用虚拟序列。例如，在SoC设计中，可能有多个不同的接口，每个接口可能需要由不同的一组序列在各自的sequencers上驱动。虚拟序列因此成为启动和控制这些不同序列的最佳方式。虚拟序列之所以‘虚拟’，是因为它不与任何特定数据类型关联。

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UVM Virtual Sequence

（实际项目中对于virtual sequence用到的频率几乎忽略不计，可以了解。）

A virtual sequence is a container to start multiple sequences on different sequencers in the environment. This virtualsequence is usually executed by a virtual sequencer which has handles to real sequencers. The need for a virtual sequencearises when you require different sequences to be run on different environments. For example, an SoC design might havemultiple different interfaces that might need to be driven by a different set of sequences on individual sequencers. Hence thebest way to start and control these different sequences would be from a virtual sequence. lt becomes virtual because it is notassociated with any particular data typ

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