HDLBitsLOG-Verilog Language

目录

-1_Preview

0_Getting Started

001_Step One

002_Output Zero

1_Basic

003_Simple Wire

004_Four Wires

005_Inverter

006_AND Gate

007_Nor Gate

008_XNOR Gate

009_Declaring Wires

010_7458 Chip

2_Vectors

011_Vectors

012_Vectors IN More Detail

013_Vector Part Select

014_Bitwise Operators

015_Four-Input Gates

016_Vector Concatenation Operator

017_Vector Reversal 1

018_Replication Operator

019_More Replication

3_Modules:Hierarchy

020_Modules

021_Connection Port By Postion

022_Connect Nets By Name

023_Three Modules

024_Modules and Vectors

025_Adder1

026_Adder2

027_Carry-Select Adder

028_Adder-Subtractor

4_Procedures

029_Always Blocks(Combinational)

030_Always Blocks(Clocked)

031_If Statement

032_If Statement Latches(😕)​

033_Case Statement Latches

034_Priority Encoder

035_Priority Encoder With Casez

036_Avoiding Latches

5_More Verilog Features

037_Conditional Ternary Operator

038_Reduction Operators

039_Reduction: Even Wider Gates

040_Combinational For-Loop: Vector Reversal 2

041_Combination For-Loop: 255-bit Population Count

042_Generate For-Loop: 100-bit binary adder 2

043_Generate For-Loop: 100-digit BCD adder

---

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-1_Preview

0_Getting Started

001_Step One

module top_module( output one );
​
// Insert your code here
    assign one = 1'b1;
​
endmodule

002_Output Zero

module top_module(
    output zero
);// Module body starts after semicolon
assign zero = 1'b0;
endmodule

1_Basic

003_Simple Wire

module top_module( input in, output out );
    assign out = in;
endmodule

004_Four Wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

005_Inverter

module top_module( input in, output out );
    assign out = ~in;
endmodule

006_AND Gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a & b;
endmodule

007_Nor Gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);
endmodule

008_XNOR Gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a^b);
    //assign out = (a&b) | (~a&~b);
endmodule

009_Declaring Wires

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    wire A1,A2,A3;
    assign A1 = a & b;
    assign A2 = c & d;
    assign A3 = A1 | A2;
    assign out = A3;
    assign out_n = ~A3;
endmodule

010_7458 Chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p2y = (p2a&p2b)|(p2c&p2d);
    assign p1y = (p1a&p1b&p1c)|(p1d&p1e&p1f);
endmodule

2_Vectors

011_Vectors

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    assign outv = vec;
    assign o2 = vec[2];
    assign o1 = vec[1];
    assign o0 = vec[0];
endmodule
​

012_Vectors IN More Detail

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    assign out_hi = in[15:8];
    assign out_lo = in[ 7:0];
endmodule

013_Vector Part Select

module top_module( 
    input [31:0] in,
    output [31:0] out );//
​
    // assign out[31:24] = ...;
    assign out[31:24] = in[ 7: 0];
    assign out[23:16] = in[15: 8];
    assign out[15: 8] = in[23:16];
    assign out[ 7: 0] = in[31:24];
    //assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule

014_Bitwise Operators

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = a | b;
    assign out_or_logical = a || b;
    assign out_not[5:0] = {~b,~a};
endmodule

015_Four-Input Gates

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and = in[3] & in[2] & in[1] & in[0];
    assign out_or =  in[3] | in[2] | in[1] | in[0];
    assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule

016_Vector Concatenation Operator

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//
​
    // assign { ... } = { ... };
    assign w = {a[4:0],b[4:2]};
    assign x = {b[1:0],c[4:0],d[4:4]};
    assign y = {d[3:0],e[4:1]};
    assign z = {e[0:0],f[4:0],2'b11};
    //assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule