Fsm onehot 答题记录

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已于 2022-07-28 14:28:49 修改 · 335 阅读

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#verilog #hdl #数字IC

于 2022-07-25 23:56:12 首次发布

该博客探讨了在Verilog中设计有限状态机（FSM）时，针对错误输入处理的三种不同策略：将所有错误归入空闲状态，设置有优先级的错误处理以及无优先级的独热码处理。每种策略通过示例代码展示，并通过错误匹配数量来评估其效果。优化后的FSM在输出匹配性和资源利用率方面有所提升。

Source:https://hdlbits.01xz.net/wiki/Fsm_onehot
题目没啥问题，只是没有描述清楚要求。
在一遍遍的提交过程中逐渐明晰
可以看ifdef的三种情况

// nodefine
// 错误输入全部归入idle
// # Hint: Output 'next_state' has 1157 mismatches. First mismatch occurred at time 1120.
// # Hint: Output 'out1' has 724 mismatches. First mismatch occurred at time 1120.
// # Hint: Output 'out2' has 744 mismatches. First mismatch occurred at time 1120.
// # Hint: Total mismatched samples is 1157 out of 1422 samples

// `define CUSTOM
// 有优先级的错误输入，低位优先级更高，具有排他性
// # Hint: Output 'next_state' has 922 mismatches. First mismatch occurred at time 1125.
// # Hint: Output 'out1' has no mismatches.
// # Hint: Output 'out2' has no mismatches.
// # Hint: Total mismatched samples is 922 out of 1422 samples

`define FINAL
// 没有优先级的独热码，可以兼容多个热码

三种不同的尝试

module top_module(
	// input clk,
    input in,
	// input rst_n,
    input  [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
	localparam 	s0 = 10'b0000_0001,
				s1 = 10'b0000_0010,
				s2 = 10'b0000_0100,
				s3 = 10'b0000_1000,
				s4 = 10'b0001_0000,
				s5 = 10'b0010_0000,
				s6 = 10'b0100_0000,
				s7 = 10'b1000_0000,
				s8 = 10'b1_0000_0000,
				s9 = 10'b10_0000_0000,
				idle = 10'b0;
	
	// nodefine
	// 错误输入全部归入idle
	// # Hint: Output 'next_state' has 1157 mismatches. First mismatch occurred at time 1120.
	// # Hint: Output 'out1' has 724 mismatches. First mismatch occurred at time 1120.
	// # Hint: Output 'out2' has 744 mismatches. First mismatch occurred at time 1120.
	// # Hint: Total mismatched samples is 1157 out of 1422 samples

	// `define CUSTOM
	// 有优先级的错误输入，低位优先级更高，具有排他性
	// # Hint: Output 'next_state' has 922 mismatches. First mismatch occurred at time 1125.
	// # Hint: Output 'out1' has no mismatches.
	// # Hint: