Verilog专题（十二）Counter Design

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1、十进制计数器（decade counter）

题目：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

 

我的设计：

    注意的点：同步复位、1为下限、10为上限。

module top_module (    input clk,    input reset,    output [3:0] q);    always@(posedge clk)begin        if(reset | q == 4'd10)            q <= 1;        else             q <= q + 1;    endendmodule​

 

2、十二进制计数器

题目：Design a 1-12 counter with the f