ERROR [BD 41-237]

AR# 56610

Vivado IP Integrator - "ERROR [BD 41-237] Bus Interface property FREQ_HZ does not match between /mig_7series/S_AXI() and interconnect_1/s00_couplers/M_AXI()"

 

描述

In a simple Vivado IP Integrator system with a mig_7series, the IP connects to an external AXI interface via a AXI Interconnect. 

However, during Generate Output Products, an error similar to the following occurs:

ERROR [BD 41-237] Bus Interface property FREQ_HZ does not match between /mig_7series/S_AXI(166250000) and interconnect_1/s00_couplers/M_AXI(10000000)

How can I fix this issue?

解决方案

If an AXI interface is made external, the FREQ_HZ property will default to 100MHz. 

As a result, you will have to manually update this in the External Interface Properties for the AXI, and the External Port Properties for the S00_ACLK.

In the example above, you need to change this to 166250000.

To change the FREQ_HZ property, highlight the external interface port in the block diagram and drop down the CONFIG, then modify the FREQ_HZ to the required Frequency in the External Port Properties GUI:

 

 

 

Repeat this for the External Port Properties too. 

Again, highlight the external clock port connected to the ACLK (in this example S00_ACLK).

 

还可参考链接：https://forums.xilinx.com/t5/Synthesis/Vivado-Synthesis-Error-BD-41-237-Bus-Interface-property-FREQ-HZ/m-p/462296#opennewwindow