Candence 数字流程

摘自：https://www.mics.ece.vt.edu/ICDesign/Tutorials/Cadence/digital_pg1.html
Front-End
Compile and Simulate: Use of NC-Verilog® and SimVision to analyze, compile and simulate an example up-down counter
Synthesis: Convert the Verilog code into gate-level netlist using Cadence’s Encounter™ RTL Compiler

1. Synthesize

a. Continue working in the same project directory as the earlier tutorial. The directory is called ‘tut_65nm’ in this tutorial.

b. Make sure you have copied rtl.tcl from the earlier tutorial. You can find the link here: rtl.tcl. This is the source script that has library path, path to >Verilog script, synthesis commands.

c. To start RTL Compiler: type ‘rc –gui’. In case, missing libraries are reported, contact sysadmin. The ‘-gui’ options pops RTL GUI. Make sure Xming is >running in case of remote connection.

d. In GUI: file → source script → load rtl.tcl → hit ‘OK’

d. On hitting ‘OK’, one should be able to observe the following:

This is the design after synthesis. The explanation of various commands executed can be referred to in the comments in rtl.tcl.

2. Reporting power and area

Power

GUI – If you are using GUI, then follow the steps: Report → Power → Detailed Report

A table as shown in figure 4 will be generated.

Command mode: report power>power.rpt

Following report is generated.

Area

GUI-If you are using GUI, then follow the steps: Report → Netlist → Area

Command mode: report area > area.rpt
3. Object browser

Object browser is a useful tool to explore the design currently loaded. It can also be used to verify the libraries being used for the design.

Tools → Object Browser

Power Estimation: TCF file generation and early power estimation of the design using SimVision and RTL Compiler.

Tool: RTL Compiler
NOTE: The files downloaded must not be saved or used in .txt format. Please save it in the format as mentioned in the tutorial.

1. Generating TCF file
   TCF (Toggle Count Format) is a proprietary format that provides switching information. Toggle attributes such as static probability (time for which net is > high to duration) and transition rate (toggle rate to duration) are used to obtain switching information for power estimation.

2. Power Estimation
   Make sure that the Cadence path has been set by typing ‘Cadence’. RTL compiler will be used to estimate power. To start, type ‘rc –gui’
   Download rtl.tcl from here: rtl.tcl and cnt_updown.sdc from here: cnt_updown.sdc. Replace the earlier rtl.tcl with this one. SDC files are constraint files. > For this tutorial the clock frequency has been set to 1 GHz.
   In GUI: File→ Source Script→ Select rtl.tcl→ hit OK
   Explanation for various commands executed by rtl.tcl can be found in the comments section of the script.

Back-End
Physical Implementation: Floorplanning to place and route of a test circuit using Cadence’s Encounter Digital Implementation.

Input Data

1. Synthesized netlist, IO pad insertion

The synthesized, IO pad inserted netlist can be downloaded from here: cnt_updown_dve.v

Explanation of the changes made:

In order to insert the pad an input signal to the pad and an output signal from the pad is required. For an input pad, the input signals are the external >signals being applied to the module whereas the output signals are the signals (wires declared in Verilog) being used by the various gates in the module. In >case of an output pad, the input signals are the modules internal signals whereas the output signals are the output signals of the module.

The library (tpdn65gpgv2od3_sdbc.lib) must be checked for appropriate cells for IO pads. These are then instantiated. The synthesized file from generated from >the synthesis stage does not have the pads instantiated by default. In order to do so, all signals going into the module can be assumed as the internal >signals. Thus, in module declaration statement additional prefix/suffix must be added to the signals to tell them apart from the signals input/output to pad >and those input/output to the module.

viewDefinition.view
This file is generally set for multi-mode multi corner analysis. But, for the purpose of this tutorial, only one view has been considered.
The file viewDefinition.view can be downloaded from here: viewDefinition.view
Timing constraint file
Having changed the synthesis file ‘cnt_updown_dve.v’ even, the sdc file constraints need to be renamed. The modified sdc file can be downloaded from here: >cnt_updown_syn.sdc
Clock specification file
This file can be downloaded from here: Clock.ctstch
Path to timing library, LEF files - theses paths may be required during import design stage.
Common timing library:

/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tcbn65gplus/tcbn65gplus_frontendzipped/tcbn65gplus_140b_nldm/
TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplusbc0d88.lib

/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd_200a_nldm/
TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpdn65gpgv2od3_sd_200a/tpdn65gpgv2od3_sdbc.lib

LEF files:
/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd_200a_sefu6lm/
TSMCHOME/digital/Back_End/lef/tpdn65gpgv2od3_sd_200a/mt_2/6lm/lef/tpdn65gpgv2od3_sd_6lm.lef

/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd/tpdn65gpgv2od3_sd_200a_sefu6lm/
TSMCHOME/digital/Back_End/lef/tpdn65gpgv2od3_sd_200a/mt_2/6lm/lef/antenna_6lm.lef

/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tcbn65gplus/tcbn65gplus_backendzipped/tcbn65gplus_200a_sef/
TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/lef/tcbn65gplus_6lmT1.lef

Capacitance table:
/software/PDK/65nm_TSMC/Mosis_Doc/65nmLibs/tcbn65gplus/tcbn65gplus_backendzipped/tcbn65gplus_200a_sef/
TSMCHOME/digital/Back_End/lef/tcbn65gplus_200a/techfiles/captable/cln65g+_1p06m+alrdl_typical_top1.captable

qrcTech file:
/software/PDK/65nm_TSMC/Mosis_Doc/65nm_general_purpose_logic_CLN65GP/T-N65-CL-SP-031-V4/T-N65-CL-SP-031-V4_12a/RC_QRC_cln65g+_1p6m_4X1Z_alrdl_5corners_12a/>RC_QRC_cln65g+_1p06m+alrdl_typical/qrcTechFile

Digital Design Flow
Digital Design Flow: Methodology for successful front-end design to back-end implementation of the chip at System on Chip (SoC) level. This involves using different tools from Synopsys and Cadence.

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以下摘自某IC设计虚拟仿真实验项目
1）逻辑仿真：ModelSim（Mentor Graphics）
2）逻辑综合：Design Compiler（Synopsys）
3）静态时序分析：Prime Time（Synopsys）
4）版图综合：SOC Encounter（Cadence）
5）自动测试矢量生成：TetraMAX（Synopsys）
6）形式验证：Formality（Synopsys）
7）版图验证工具：IC5141、Assura （Cadence）