【【RTC实时时钟实验 -- 在HDMI上显示-FPGA 小实验】】

本文链接：https://blog.youkuaiyun.com/weixin_50965981/article/details/135438332

RTC实时时钟实验 – 在HDMI上显示

top.v

module RTS_TOP#(
    parameter   TIME_INIT   =   48'h24_01_06_11_08_00     ,
    parameter   WAIT_TIME   =   13'd8000                  ,
    parameter   SLAVE_ADDR  =   7'b1010001                , // E2PROM 浠庢満鍦板潃
    parameter   CLK_FREQ    =   26'd50_000_000            , // 50MHz 鐨勬椂閽熼锟�?
    parameter   I2C_FREQ    =   18'd250_000                 // SCL 鐨勬椂閽熼锟�?     
)(
    input                            sys_clk       ,
    input                            rst_n         ,
    
    // to HDMI 
    output       tmds_clk_p                    ,    // TMDS 鏃堕挓閫氶亾
    output       tmds_clk_n                    ,
    output [2:0] tmds_data_p                   ,   // TMDS 鏁版嵁閫氶亾
    output [2:0] tmds_data_n                   ,

    // I2C 閫氶亾
    output                         scl      ,
    inout                             sda
);
//-----------------------------------------------------
//-----------------------------------------------------
// next   is  wire  and  reg  define  

wire      [15 : 0]   i2c_addr      ;
wire      [7  : 0]   i2c_data_w    ;                    
wire                 i2c_rh_wl     ;                     
wire                 i2c_exec      ;      
wire                 dri_clk       ;
wire      [7  : 0]   i2c_data_r    ;
wire                 i2c_ack       ;
wire                 i2c_done      ;

wire      [7 : 0 ]   sec           ;
wire      [7 : 0 ]   min           ;
wire      [7 : 0 ]   hour          ;
wire      [7 : 0 ]   day           ;
wire      [7 : 0 ]   mon           ;
wire      [7 : 0 ]   year          ;                           
                        
                              
            





//--------------------------------------------------------
//--------------------------------------------------------

IIC_CONTROL#(
    .SLAVE_ADDR   ( 7'b1010001 ),
    .CLK_FREQ     ( 26'd50_000_000 ),
    .I2C_FREQ     ( 18'd250_000 )
)u_IIC_CONTROL(
    .clk          ( sys_clk          ),
    .rst_n        ( rst_n        ),
    .i2c_addr     ( i2c_addr     ),
    .i2c_data_w   ( i2c_data_w   ),
    .i2c_rh_wl    ( i2c_rh_wl    ),
    .bit_control  ( 0  ),
    .i2c_exec     ( i2c_exec     ),
    .dri_clk      ( dri_clk      ),
    .i2c_data_r   ( i2c_data_r   ),
    .i2c_ack      ( i2c_ack      ),
    .i2c_done     ( i2c_done     ),
    .scl          ( scl          ),
    .sda          (  sda    )
);

PCF8563#(
    .TIME_INIT   ( TIME_INIT ),
    .WAIT_TIME   ( WAIT_TIME )
)u_PCF8563(
    .clk         ( dri_clk         ),
    .rst_n       ( rst_n       ),
    .i2c_done    ( i2c_done    ),
    .i2c_data_r  ( i2c_data_r  ),
    .i2c_rh_wl   ( i2c_rh_wl   ),
    .i2c_exec    ( i2c_exec    ),
    .i2c_addr    ( i2c_addr    ),
    .i2c_data_w  ( i2c_data_w  ),
    .sec         ( sec         ),
    .min         ( min         ),
    .hour        ( hour        ),
    .day         ( day         ),
    .mon         ( mon         ),
    .year        ( year        )
);




hdmi_top u_hdmi_top(
    .sys_clk      ( sys_clk      ),
    .sys_rst_n    ( rst_n    ),
    .tmds_clk_p   ( tmds_clk_p   ),
    .tmds_clk_n   ( tmds_clk_n   ),
    .tmds_data_p  ( tmds_data_p  ),
    .tmds_data_n  ( tmds_data_n  ),
    .sec          ( sec          ),
    .min          ( min          ),
    .hour         ( hour         ),
    .day          ( day          ),
    .mon          ( mon          ),
    .year         ( year         )
);


endmodule

dvi_transmitter_top.v

module dvi_transmitter_top(
    input                pclk          ,
    input                sys_rst_n     ,
    input                pclk_x5       ,
    input                video_hsync   ,
    input                video_vsync   ,
    input                video_de      ,
    input   [23 : 0]     video_din     ,
    output               tmds_clk_p    ,
    output               tmds_clk_n    ,
    output  [2 : 0]      tmds_data_p   ,
    output  [2 : 0]      tmds_data_n   ,
    output               tmds_oen  
);


assign tmds_oen = 1 ; 

// next is  define  
wire  reset ;
wire [9:0] blue_10bit ;
wire [9:0] green_10bit ;
wire [9:0] red_10bit ;


wire [2:0] tmds_data_serial ; 
wire       tmds_clk_serial  ;



reset_syn u_reset_syn(
    .pclk     ( pclk     ),
    .reset_n  ( sys_rst_n  ),
    .reset    ( reset    )
);


dvi_encoder u_dvi_encoder_blue(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[7:0]   ),
    .c0    ( video_hsync    ),
    .c1    ( video_vsync    ),
    .de    ( video_de    ),
    .dout  ( blue_10bit  )
);

dvi_encoder u_dvi_encoder_green(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[15:8]   ),
    .c0    ( 1'b0    ),
    .c1    ( 1'b0    ),
    .de    ( video_de    ),
    .dout  ( green_10bit  )
);


dvi_encoder u_dvi_encoder_red(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[23:16]   ),
    .c0    ( 1'b0    ),
    .c1    ( 1'b0    ),
    .de    ( video_de    ),
    .dout  ( red_10bit  )
);

serializer10 u_serializer10_blue(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( blue_10bit  ),
    .serial_data_out  ( tmds_data_serial[0]  )
);

serializer10 u_serializer10_green(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( green_10bit  ),
    .serial_data_out  ( tmds_data_serial[1]  )
);

serializer10 u_serializer10_red(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( red_10bit  ),
    .serial_data_out  ( tmds_data_serial[2]  )
);

serializer10 u_serializer10_clk(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( 10'b1111100000  ),
    .serial_data_out  ( tmds_clk_serial  )
);


//转换差分信号  
OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS0 (
    .I                  (tmds_data_serial[0]),
    .O                  (tmds_data_p[0]),
    .OB                 (tmds_data_n[0]) 
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS1 (
    .I                  (tmds_data_serial[1]),
    .O                  (tmds_data_p[1]),
    .OB                 (tmds_data_n[1]) 
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS2 (
    .I                  (tmds_data_serial[2]), 
    .O                  (tmds_data_p[2]), 
    .OB                 (tmds_data_n[2])  
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS3 (
    .I                  (tmds_clk_serial), 
    .O                  (tmds_clk_p),
    .OB                 (tmds_clk_n) 
);
endmodule

encoder.v

module dvi_encoder (
  input            clkin,    // pixel clock input
  input            rstin,    // async. reset input (active high)
  input      [7:0] din,      // data inputs: expect registered
  input            c0,       // c0 input
  input            c1,       // c1 input
  input            de,       // de input
  output reg [9:0] dout      // data outputs
);

  
  // Counting number of 1s and 0s for each incoming pixel
  // component. Pipe line the result.
  // Register Data Input so it matches the pipe lined adder
  // output
  
  reg [3:0] n1d; //number of 1s in din
  reg [7:0] din_q;

//计算像素数据中“1”的个数
  always @ (posedge clkin) begin
    n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7];

    din_q <=#1 din;
  end

  ///
  // Stage 1: 8 bit -> 9 bit
  // Refer to DVI 1.0 Specification, page 29, Figure 3-5
  ///
  wire decision1;

  assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0));

  wire [8:0] q_m;
  assign q_m[0] = din_q[0];
  assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]);
  assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]);
  assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]);
  assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]);
  assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]);
  assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]);
  assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]);
  assign q_m[8] = (decision1) ? 1'b0 : 1'b1;

  /
  // Stage 2: 9 bit -> 10 bit
  // Refer to DVI 1.0 Specification, page 29, Figure 3-5
  /
  reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m
  always @ (posedge clkin) begin
    n1q_m  <=#1 q_m[0] + q_m[1] + q_m[2] + q_m