【【ZYNQ7020 HDMI 显示文字实验】】

已于 2023-12-15 13:12:36 修改
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分类专栏： 图像学习 FPGA学习 文章标签： fpga开发
于 2023-12-14 19:19:40 首次发布
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ZYNQ7020 HDMI 显示文字实验

dvi_transmitter_top.v

module dvi_transmitter_top(
    input                pclk          ,
    input                sys_rst_n     ,
    input                pclk_x5       ,
    input                video_hsync   ,
    input                video_vsync   ,
    input                video_de      ,
    input   [23 : 0]     video_din     ,
    output               tmds_clk_p    ,
    output               tmds_clk_n    ,
    output  [2 : 0]      tmds_data_p   ,
    output  [2 : 0]      tmds_data_n   ,
    output               tmds_oen  
);


assign tmds_oen = 1 ; 

// next is  define  
wire  reset ;
wire [9:0] blue_10bit ;
wire [9:0] green_10bit ;
wire [9:0] red_10bit ;


wire [2:0] tmds_data_serial ; 
wire       tmds_clk_serial  ;



reset_syn u_reset_syn(
    .pclk     ( pclk     ),
    .reset_n  ( sys_rst_n  ),
    .reset    ( reset    )
);


dvi_encoder u_dvi_encoder_blue(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[7:0]   ),
    .c0    ( video_hsync    ),
    .c1    ( video_vsync    ),
    .de    ( video_de    ),
    .dout  ( blue_10bit  )
);

dvi_encoder u_dvi_encoder_green(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[15:8]   ),
    .c0    ( 1'b0    ),
    .c1    ( 1'b0    ),
    .de    ( video_de    ),
    .dout  ( green_10bit  )
);


dvi_encoder u_dvi_encoder_red(
    .clkin ( pclk ),
    .rstin ( reset ),
    .din   ( video_din[23:16]   ),
    .c0    ( 1'b0    ),
    .c1    ( 1'b0    ),
    .de    ( video_de    ),
    .dout  ( red_10bit  )
);

serializer10 u_serializer10_blue(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( blue_10bit  ),
    .serial_data_out  ( tmds_data_serial[0]  )
);

serializer10 u_serializer10_green(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( green_10bit  ),
    .serial_data_out  ( tmds_data_serial[1]  )
);

serializer10 u_serializer10_red(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( red_10bit  ),
    .serial_data_out  ( tmds_data_serial[2]  )
);

serializer10 u_serializer10_clk(
    .reset          ( reset          ),
    .paralell_clk   ( pclk   ),
    .serial_clk_5x  ( pclk_x5  ),
    .paralell_data  ( 10'b1111100000  ),
    .serial_data_out  ( tmds_clk_serial  )
);


//转换差分信号  
OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS0 (
    .I                  (tmds_data_serial[0]),
    .O                  (tmds_data_p[0]),
    .OB                 (tmds_data_n[0]) 
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS1 (
    .I                  (tmds_data_serial[1]),
    .O                  (tmds_data_p[1]),
    .OB                 (tmds_data_n[1]) 
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS2 (
    .I                  (tmds_data_serial[2]), 
    .O                  (tmds_data_p[2]), 
    .OB                 (tmds_data_n[2])  
);

OBUFDS #(
    .IOSTANDARD         ("TMDS_33")    // I/O电平标准为TMDS
) TMDS3 (
    .I                  (tmds_clk_serial), 
    .O                  (tmds_clk_p),
    .OB                 (tmds_clk_n) 
);
endmodule

encoder.v

module dvi_encoder (
  input            clkin,    // pixel clock input
  input            rstin,    // async. reset input (active high)
  input      [7:0] din,      // data inputs: expect registered
  input            c0,       // c0 input
  input            c1,       // c1 input
  input            de,       // de input
  output reg [9:0] dout      // data outputs
);

  
  // Counting number of 1s and 0s for each incoming pixel
  // component. Pipe line the result.
  // Register Data Input so it matches the pipe lined adder
  // output
  
  reg [3:0] n1d; //number of 1s in din
  reg [7:0] din_q;

//计算像素数据中“1”的个数
  always @ (posedge clkin) begin
    n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7];

    din_q <=#1 din;
  end

  ///
  // Stage 1: 8 bit -> 9 bit
  // Refer to DVI 1.0 Specification, page 29, Figure 3-5
  ///
  wire decision1;

  assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0));

  wire [8:0] q_m;
  assign q_m[0] = din_q[0];
  assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]);
  assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]);
  assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]);
  assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]);
  assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]);
  assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]);
  assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]);
  assign q_m[8] = (decision1) ? 1'b0 : 1'b1;

  /
  // Stage 2: 9 bit -> 10 bit
  // Refer to DVI 1.0 Specification, page 29, Figure 3-5
  /
  reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m
  always @ (posedge clkin) begin
    n1q_m  <=#1 q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7];
    n0q_m  <=#1 4'h8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]);
  end

  parameter CTRLTOKEN0 = 10'b1101010100;
  parameter CTRLTOKEN1 = 10'b0010101011;
  parameter CTRLTOKEN2 = 10'b0101010100;
  parameter CTRLTOKEN3 = 10'b1010101011;

  reg [4:0] cnt; //disparity counter, MSB is the sign bit
  wire decision2, decision3;

  assign decision2 = (cnt == 5'h0) | (n1q_m == n0q_m);
  /
  // [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)]
  /
  assign decision3 = (~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m));

  
  // pipe line alignment
  
  reg       de_q, de_reg;
  reg       c0_q, c1_q;
  reg       c0_reg, c1_reg;
  reg [8:0] q_m_reg;

  always @ (posedge clkin) begin
    de_q    <=#1 de;
    de_reg  <=#1 de_q;
    
    c0_q    <=#1 c0;
    c0_reg  <=#1 c0_q;
    c1_q    <=#1 c1;
    c1_reg  <=#1 c1_q;

    q_m_reg <=#1 q_m;
  end

  ///
  // 10-bit out
  // disparity counter
  ///
  always @ (posedge clkin or posedge rstin) begin
    if(rstin) begin
      dout <= 10'h0;
      cnt <= 5'h0;
    end else begin
      if (de_reg) begin
        if(decision2) begin
          dout[9]   <=#1 ~q_m_reg[8]; 
          dout[8]   <=#1 q_m_reg[8]; 
          dout[7:0] <=#1 (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0];

          cnt <=#1 (~q_m_reg[8]) ? (cnt + n0q_m - n1q_m) : (cnt + n1q_m - n0q_m);
        end else begin
          if(decision3) begin
            dout[9]   <=#1 1'b1;
            dout[8]   <=#1 q_m_reg[8];
            dout[7:0] <=#1 ~q_m_reg[7:0];

            cnt <=#1 cnt + {q_m_reg[8], 1'b0} + (n0q_m - n1q_m);
          end else begin
            dout[9]   <=#1 1'b0;
            dout[8]   <=#1 q_m_reg[8];
            dout[7:0] <=#1 q_m_reg[7:0];

            cnt <=#1 cnt - {~q_m_reg[8], 1'b0} + (n1q_m - n0q_m);
          end
        end
      end else begin
        case ({c1_reg, c0_reg})
          2'b00:   dout <=#1 CTRLTOKEN0;
          2'b01:   dout <=#1 CTRLTOKEN1;
          2'b10:   dout <=#1 CTRLTOKEN2;
          default: dout <=#1 CTRLTOKEN3;
        endcase

        cnt <=#1 5'h0;
      end
    end
  end
  
endmodule

reset_syn.v

module  reset_syn(
    input            pclk     ,
    input            reset_n  ,
    output   reg     reset
  );

  reg reset1 ;


  always@( posedge pclk   or  negedge reset_n)
  begin
    if( reset_n == 0)
    begin
      reset1 <= 1 ;
    end
    else
    begin
      reset1 <= 0      ;
      reset  <= reset1 ;
    end
  end
endmodule

serializer.v

module serializer10 (
    input                       reset           ,  // 复位,高有效
    input                       paralell_clk    ,  // 输入并行数据时钟 
    input                       serial_clk_5x   ,   // 输入串行数据时钟
    input        [9 : 0]        paralell_data   ,   // 输入并行数据
    output                      serial_data_out          // 输出串行数据
);



//wire define
 wire cascade1 ; //用于两个 OSERDESE2 级联的信号
 wire cascade2 ;



// 此处的代码 来自 vivado的 原语 和 正点原子的同时调配 
// 这是 master接口 



OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),   // 设置双倍数据速率
    .DATA_RATE_TQ("DDR"),   // DDR, BUF, SDR
    .DATA_WIDTH(10),         // 输入的并行数据宽度为 10bit
   // .INIT_OQ(1'b0),         // Initial value of OQ output (1'b0,1'b1)
   // .INIT_TQ(1'b0),         // Initial value of TQ output (1'b0,1'b1)
    .SERDES_MODE("MASTER"), // MASTER, SLAVE
    //.SRVAL_OQ(1'b0),        // OQ output value when SR is used (1'b0,1'b1)
   // .SRVAL_TQ(1'b0),        // TQ output value when SR is used (1'b0,1'b1)
    .TBYTE_CTL("FALSE"),    // Enable tristate byte operation (FALSE, TRUE)
    .TBYTE_SRC("FALSE"),    // Tristate byte source (FALSE, TRUE)
    .TRISTATE_WIDTH(1)      // 3-state converter width (1,4)
 )
 OSERDESE2_MASTER (
    .OFB(),             // 未使用
    .OQ(serial_data_out),               // 串行输出数据
    // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
    .SHIFTOUT1(),  // SHIFTIN1 用于位宽扩展
    .SHIFTOUT2(),  // SHIFTIN2 用于位宽扩展
    .TBYTEOUT(),   // 未使用
    .TFB(),             // 未使用
    .TQ(),               // 未使用
    .CLK(serial_clk_5x),    // 串行数据时钟,5 倍时钟频率
    .CLKDIV(paralell_clk),  // 并行数据时钟
    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
    .D1(paralell_data[0]),
    .D2(paralell_data[1]),
    .D3(paralell_data[2]),
    .D4(paralell_data[3]),
    .D5(paralell_data[4]),
    .D6(paralell_data[5]),
    .D7(paralell_data[6]),
    .D8(paralell_data[7]),
    .OCE(1'b1),             // 1-bit input: Output data clock enable
    .RST(reset),             // 1-bit input: Reset
    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
    .SHIFTIN1(cascade1),     // SHIFTIN1 用于位宽扩展
    .SHIFTIN2(cascade2),     // SHIFTIN2  用于位宽扩展
    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
    .T1(1'b0),                // 未使用
    .T2(1'b0),                // 未使用
    .T3(1'b0),                // 未使用
    .T4(1'b0),                // 未使用
    .TBYTEIN(1'b0),     // 未使用
    .TCE(1'b0)              // 未使用
 );


// slave接口 
 OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),   // 设置双倍数据速率
    .DATA_RATE_TQ("DDR"),   // DDR, BUF, SDR
    .DATA_WIDTH(10),         // 输入的并行数据宽度为 10bit
   // .INIT_OQ(1'b0),         // Initial value of OQ output (1'b0,1'b1)
   // .INIT_TQ(1'b0),         // Initial value of TQ output (1'b0,1'b1)
    .SERDES_MODE("SLAVE"), // MASTER, SLAVE
    //.SRVAL_OQ(1'b0),        // OQ output value when SR is used (1'b0,1'b1)
   // .SRVAL_TQ(1'b0),        // TQ output value when SR is used (1'b0,1'b1)
    .TBYTE_CTL("FALSE"),    // Enable tristate byte operation (FALSE, TRUE)
    .TBYTE_SRC("FALSE"),    // Tristate byte source (FALSE, TRUE)
    .TRISTATE_WIDTH(1)      // 3-state converter width (1,4)
 )
 OSERDESE2_SLAVE (
    .OFB(),             // 未使用
    .OQ(),               // 串行输出数据
    // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
    .SHIFTOUT1(cascade1),  // SHIFTIN1 用于位宽扩展
    .SHIFTOUT2(cascade2),  // SHIFTIN2 用于位宽扩展
    .TBYTEOUT(),   // 未使用
    .TFB(),             // 未使用
    .TQ(),               // 未使用
    .CLK(serial_clk_5x),    // 串行数据时钟,5 倍时钟频率
    .CLKDIV(paralell_clk),  // 并行数据时钟
    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
    .D1(1'b0),
    .D2(1'b0),
    .D3(paralell_data[8]),
    .D4(paralell_data[9]),
    .D5(1'b0),
    .D6(1'b0),
    .D7(1'b0),
    .D8(1'b0),
    .OCE(1'b1),             // 1-bit input: Output data clock enable
    .RST(reset),             // 1-bit input: Reset
    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
    .SHIFTIN1(),     // SHIFTIN1 用于位宽扩展
    .SHIFTIN2(),     // SHIFTIN2  用于位宽扩展
    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
    .T1(1'b0),                // 未使用
    .T2(1'b0),                // 未使用
    .T3(1'b0),                // 未使用
    .T4(1'b0),                // 未使用
    .TBYTEIN(1'b0),     // 未使用
    .TCE(1'b0)              // 未使用
 );

endmodule

top.v

module hdmi_top(
    input        sys_clk,
    input        sys_rst_n,

    output       tmds_clk_p,    // TMDS 时钟通道
    output       tmds_clk_n,
    output [2:0] tmds_data_p,   // TMDS 数据通道
    output [2:0] tmds_data_n
  );

  //wire define
  wire          pixel_clk;
  wire          pixel_clk_5x;
  wire          clk_locked;

  wire  [10:0]  pixel_xpos_w;
  wire  [10:0]  pixel_ypos_w;
  wire  [23:0]  pixel_data_w;

  wire          video_hs;
  wire          video_vs;
  wire          video_de;
  wire  [23:0]  video_rgb;

  // next is main code
  clk_wiz_0 instance_name
            (
              // Clock out ports
              .clk_out1(pixel_clk),     // output clk_out1
              .clk_out2(pixel_clk_5x),     // output clk_out2
              // Status and control signals
              .reset(~sys_rst_n), // input reset
              .locked(clk_locked),       // output locked
              // Clock in ports
              .clk_in1(sys_clk)
              );

video_driver u_video_driver(
    .pixel_clk   ( pixel_clk   ),
    .rst_n       ( sys_rst_n       ),
    .pixel_data  ( pixel_data_w  ),
    .video_rgb   ( video_rgb   ),
    .video_hs    ( video_hs    ),
    .video_vs    ( video_vs    ),
    .video_de    ( video_de    ),
    .pixel_xpos  ( pixel_xpos_w  ),
    .pixel_ypos  ( pixel_ypos_w  )
);

video_display u_video_display(
    .pixel_clk     ( pixel_clk     ),
    .sys_rst_n     ( sys_rst_n     ),
    .pixel_xpos_w  ( pixel_xpos_w  ),
    .pixel_ypos_w  ( pixel_ypos_w  ),
    .pixel_data_w  ( pixel_data_w  )
);


dvi_transmitter_top u_dvi_transmitter_top(
    .pclk         ( pixel_clk         ),
    .sys_rst_n    ( sys_rst_n & clk_locked    ),
    .pclk_x5      ( pixel_clk_5x      ),
    .video_hsync  ( video_hs  ),
    .video_vsync  ( video_vs  ),
    .video_de     ( video_de     ),
    .video_din    ( video_rgb    ),
    .tmds_clk_p   ( tmds_clk_p   ),
    .tmds_clk_n   ( tmds_clk_n   ),
    .tmds_data_p  ( tmds_data_p  ),
    .tmds_data_n  ( tmds_data_n  ),
    .tmds_oen     ( )
);

endmodule

video_display.v

module video_display(
    input                     pixel_clk       ,
    input                     sys_rst_n       ,
    input       [ 11 : 0 ]    pixel_xpos_w    ,
    input       [ 11 : 0 ]    pixel_ypos_w    ,
    output reg  [ 23 : 0 ]    pixel_data_w
  );


//parameter define 
  localparam CHAR_X_START= 11'd1;      //字符起始点横坐标
  localparam CHAR_Y_START= 11'd110;    //字符起始点纵坐标
  localparam CHAR_WIDTH  = 11'd640;    //字符宽度,4个字�?:32*4
  localparam CHAR_HEIGHT = 11'd64;     //字符高度


  //棰滆�?
  localparam BACK_COLOR  = 24'hE0FFFF; //背景色，浅蓝�?
  localparam CHAR_COLOR  = 24'hff0000; //字符颜色，红�?


  wire  [10:0]  x_cnt;       //横坐标计数器
  wire  [10:0]  y_cnt;       //纵坐标计数器
  reg   [639:0] char[63:0];  //字符数组
  assign  x_cnt = pixel_xpos_w - CHAR_X_START; //像素点相对于字符区域起始点水平坐�?
  assign  y_cnt = pixel_ypos_w - CHAR_Y_START; //像素点相对于字符区域起始点垂直坐�?

  always @(posedge pixel_clk) begin

char[ 0]  <=  640'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
char[ 1]  <=  640'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
char[ 2]  <=  640'h0002000000000000000000000000000000000000000000000000000800000000000000040000000000000000000000000000800000000000000000180000000000000000000000000000000000000000;
char[ 3]  <=  640'h00038000000000000000700000000000000020000000000000000006000000000000000F0000000000000000000000000001E00000C000000000000E0000000000000000008000000000001800000000;
char[ 4]  <=  640'h0007E000000000000000780006000000000038000000000000000007000000000000000F8000000000000000020000000001F00001E0000000000007800000000000000000E000000000000E00000000;
char[ 5]  <=  640'h00078000000000000000FC000780000000003E000000000000000003C00000000000001F800000000030000003C000000003E00001F0000000000003C00000000000000000F800000000000F80000000;
char[ 6]  <=  640'h00070000000000000001F80007C0000000003E000000000000000001E00000000000001F00000000001C000003F000000003C00001E0000000000003E00000000000040001F8000000000007C0000000;
char[ 7]  <=  640'h00070006000002000001E0000780000000003C000000000000000001E00000000000003F80000000000F000003E000000003800603C0000000000001F000000000000E0001F0000000000003E0000000;
char[ 8]  <=  640'h000E000F030007000003C0000700100000003C000000000000000000F00000000000003CC00000000007800003C000000007800F0380018000000001F00000000FFFFF0001F0000000000003E0000000;
char[ 9]  <=  640'h000FFFFF83FFFF80000780000700380000003C000000000000000000F00000000000007C400000000003C00003C000000007FFFF870003C000000000F000000007FFFF8003D8000000300001E0000000;
char[10 ]  <=  640'h000FFFFFC3FFFFC00007008007007C0000003C000000000000040000F000000000000078600000000003E00003C00000000FFFFFC7FFFFE000300000F000000002000E0003C8000000300001C0000200;
char[11 ]  <=  640'h001C0F0003800780000E00600700FE0000003C000000000000040000E0000600000000F8300000000001F00003C00000000E0C000FFFFFF000300000E000010000000E00078C000000300000C0000700;
char[12 ]  <=  640'h00180F0003800700001C00700701F80000003C0000000000000C000040000F00000001F0380000000001F00003C00000001C07000E030000003000004000038000001E00070C0000003FFFFFFFFFFF80;
char[13 ]  <=  640'h00380F00038007000038003C0707E00000003C0000000000000FFFFFFFFFFF80000001E01C0000000000F00003C00000003C07801C01E000003FFFFFFFFFFFC000001E000F060000007FFFFFFFFFFFC0;
char[14 ]  <=  640'h00300E00038007000070001E070F000000003C0000000600000FFFFFFFFFFFC0000003C00E0000000000E00003C00000003803C03800F000003FFFFFFFFFFFE000601E000E0600000070000000000F80;
char[ 15]  <=  640'h00600E000380070000E0001F073C000000003C0000000F00001C000000000F80000007C0070000000000000003C00000007003C03000F80000700000000007F000781C001E0300000070000000000E00;
char[16 ]  <=  640'h00C00E000380070001C0000F07F0018000003FFFFFFFFF80001C000000001E0000000780078000000000000003C0000000E003C06000780000700000000007C000781C001C03800000F0000000001C00;
char[17 ]  <=  640'h00800E000380070007FFFFFF8780018000003FFFFFFFFFC0003C000000001C0000000F0003C000000000000003C0000000C00180C000380000F0000020000F0000701C003801C00001F0000000001800;
char[18 ]  <=  640'h00000E018380070003FFFF07870001800000380000000000007C00000000180000001E0001E000000000000003C00000018180018003B00000F0180038000E0000701C003801C00003F0000000003000;
char[19 ]  <=  640'h00000E03C380070003FE000787000180000038000000000000FC00200000300000003C0000F800000000000003C000000301FFFFFFFFC00001F00E003E00180000F01C007000E00003E0000000032000;
char[20 ]  <=  640'h0FFFFFFFE380070001C0000707000180000038000000000001F800380000200000007C00007C00000000000003C000000601FFFFFFFFC00003F007803F00100000F01C00E000F00003C0000000078000;
char[21 ]  <=  640'h07FFFFFFF3800700010000020700018000007800000000000070003E0000400000007800003F00000000000003C000000C01E0000007800003E007E03E00200000E03C00E0007800001FFFFFFFFFC000;
char[ 22]  <=  640'h02001C000380070000000000070001C000007800000000000000003E000000000000F000001FC0000000000003C000800001E0000007800003C003F03C00200000E03C01C0003E00000FFFFFFFFFE000;
char[ 23]  <=  640'h00001C000380070000000020070001C000007800000000000000007C000000000001E000000FF0000001000003C001C00001E00000078000000001F03C00000000E03C0380001F000000001F00000000;
char[ 24]  <=  640'h00003E000380070000C00030078003E0000078000000000000000078000000000003C000000FFE000003800003C003E00001E00000078000000000F03C00000000E0380700005FC00000003E00000000;
char[ 25]  <=  640'h00003F800380070000FFFFFC07FFFFF00000780000000000000000780000000000070000001FFFC03FFFC7FFFFFFFFF00001FFFFFFFF8000000000F03C00000000E038060000CFF80000007C00000000;
char[26 ]  <=  640'h000038F003FFFF0000FFFFFC03FFFFE00000780000000000000000F000000300001FFFFFFFFFFFF81FFFE3FFFFFFFFF80001FFFFFFFF8000000000703C00000000E0380C0001E7F0000000F000400000;
char[27 ]  <=  640'h0000787C03FFFF0000F0007801FFFF800000780000000C00000000F000000780003DFFFFFFFFBFE00C07818003C000000001E00000078000000000603C00000001E0381BFFFFF3C0000001E000300000;
char[28 ]  <=  640'h0000F03F0380070000F00078000000000000780000001E00000000E000000FC000708003C0000FC00007800003C000000001E00000078000000700203C00000001E03831FFFFF880000003C0003C0000;
char[29 ]  <=  640'h0000E01F8380070000F00078000000000000FFFFFFFFFF000FFFFFFFFFFFFFE000E00003C00003800007800003C000000001E000000780000003C0003C00000001C03860C000000000000700001E0000;
char[30 ]  <=  640'h0001E00F8380078000F00078000000000001FFFFFFFFFF0007FFFFFFFFFFFFF003800003C00000000007800003C000000001E000000780000001F0003C00000001C078400000000000000E00000F8000;
char[ 31]  <=  640'h0003C0078380060000F00078080000000000F80000001E00000001C0003E000006000003C00000000007800003C000000001FFFFFFFF80000001F8007800000001C079800000000000003C000007C000;
char[ 32]  <=  640'h000780038200000000F000780E0000000000300000001C00000003C0003C000018000003C00000000007800003C000000001FFFFFFFF80000000FC007800000003FFFFC0000008000000F0000007E000;
char[ 33]  <=  640'h000F00018000000000FFFFF80F8008000000000000001C0000000380007C000000000003C00000000007800003C000000001E0000007800000007C007800000003FFFFF004000C000007E0000003E000;
char[ 34]  <=  640'h001C40018000000000FFFFF80F801C000000000000001C00000007800078000000000003C00000000007800003C000000001E0000007800000003C007800000001C003C006001F000003FFFFFFFFF000;
char[ 35]  <=  640'h003830000001800000F000780F001E000000000000001C000000070000F8000000000003C00000000007800003C000000001E0000007800000003C00780000000080038402001F800003FFFFF801F000;
char[ 36]  <=  640'h00E03FFFFFFFC00000F000780F003E000000000000001C0000000F0000F0000000000003C00000000007800003C000000001E0000007800000001C00780001000000038203001F000001FF020000F000;
char[37]   <= 640'h0803FFFFFFFE00000F000780F007F000000000000003C0000000E0001F0000000000003C00000000007800003C000000001E0000007800000001800780003800000038303801E000001E0038000E000;
char[ 38]  <=  640'h060038000003C00000F000780F00F8000000000000003C0000001E0001E0000000000003C00300000007800003C000000001FFFFFFFF800000000800F00007C00000038301C01C0000000003E0006000;
char[39 ]  <=  640'h000038000003800000F000780F03E0000000000000803C0000001C0003E0000000000003C00780000007800003C000000001FFFFFFFF80000FFFFFFFFFFFFFE00000038381C03C0000000003E0004000;
char[40 ]  <=  640'h000038000003800000F000780F07C0000000000001C03C0000003C0003C00000000FFFFFFFFFC0000007800003C000000001E1E003C7800007FFFFFFFFFFFFF000000381C1E0380000000003C0000000;
char[41 ]  <=  640'h000038000003800000F000780F0F00000000000003E03C0000003800078000000007FFFFFFFFE0000007800003C000000001E1E003C7000002000000F000000000000381C0E0380000000003C0000000;
char[ 42]  <=  640'h000038000003800000FFFFF80F3C00000FFFFFFFFFF03C00000078000780000000030003C00000000007800003C00000000181E003C4000000000001E00000000001F781E0F0780000000003C0018000;
char[ 43]  <=  640'h000038000003800000FFFFF80F70000007FFFFFFFFF83C0000007F800F00000000000003C00000000007806003C00000000001C003C0000000000001E0000000007F8781E0F0700000000003C003C000;
char[ 44]  <=  640'h000038000003800000F000780FC000000200000000003800000003FC1F00000000000003C0000000000780C003C00000000001C003C0008000000001C00000003FFC0781F0F07000000FFFFFFFFFE000;
char[ 45]  <=  640'h00003FFFFFFF800000F000780F00000000000000000038000000007FBE00000000000003C00000000007818003C00000000001C003C001C000000003E00000001FE00700F0F060000007FFFFFFFFF000;
char[ 46]  <=  640'h00003FFFFFFF800000F000780F000080000000000000780000000007FC00000000000003C00000000007830003C00000000003C003C003E000000007FE0000000F000700F0F0E00000020003C0000000;
char[47 ]  <=  640'h000038000003800000F000780F000080000000000000780000000000FF00000000000003C00000000007870003C00000000003C003FFFFF0000000079FC000000C000700F070C00000000003C0000000;
char[48 ]  <=  640'h000038000003800000F000780F000080000000000000780000000000FFE0000000000003C000000000078E0003C000000FFFFFFFFFFFFFF80000000F87F0000000000700F060C00000000003C0000000;
char[49 ]  <=  640'h000038000003800000F000780F0000C0000000000000780000000001F7FC000000000003C000000000079C0003C00000070003C003C000000000001F01FE000000000F00F001C00000000003C0000000;
char[50 ]  <=  640'h000038000003800000F000780F0000C0000000000000780000000003E1FF000000000003C00000000007F80003C000000000078003C000000000003E007F800000000F00E001800000000003C0000000;
char[51 ]  <=  640'h000038000003800000F000780F0000C0000000000000F00000000007C03FC00000000003C00000000007F80003C000000000078003C000000000007C003FE00000000F004001800000000003C0000000;
char[52 ]  <=  640'h000038000003800000F000780F0000C0000000000000F0000000001F000FF80000000003C00000000007F00003C0000000000F0003C00000000000F8000FF80000000E000001000000000003C0000000;
char[ 53]  <=  640'h000038000003800000F000780F0000E0000000000001F0000000007E0003FC0000000003C00002000007E00003C0000000000F0003C00000000003F00003FC0000C01E000003008000000003C0000180;
char[ 54]  <=  640'h00003FFFFFFF800000F000780F0001E0000000003C03E000000001F80001FE0000000003C0000700000FE00003C0000000001E0003C0000000000FC00001FE00007E3E00000301C000000003C00003C0;
char[55]   <=  640'h0003FFFFFFF800000F07FF00F8001F8000000001FFFE000000007E000007F0000000003C0000F800007C00003C0000000003C0003C0000000003F800000FE00001FFC00000203E000000003C00007E0;
char[56 ]  <=  640'h000038000003800000F01FF007FFFFF00000000003FFC00000001F8000003F8007FFFFFFFFFFFFC00003800003C000000000F80003C000000000FC0000007E000007F87FFFFFFFF01FFFFFFFFFFFFFF0;
char[57 ]  <=  640'h000038000003800000F007F007FFFFE00000000000FF80000000FE0000001F8003FFFFFFFFFFFFE00001800003C000000001E00003C000000007F00000001E000003F83FFFFFFFF80FFFFFFFFFFFFFF8;
char[58 ]  <=  640'h000038000003800000F003E001FFFF8000000000007F0000000FE0000000078001000000000000000000000003C000000007800003C00000003F800000001E000001E018000000000600000000000000;
char[59 ]  <=  640'h000030000003800000E001C00000000000000000003E000000FF00000000010000000000000000000000000003C00000003E000003C0000003F800000000060000018000000000000000000000000000;
char[60 ]  <=  640'h00004000000200000080018000000000000000000030000007C00000000000000000000000000000000000000200000000F00000038000000F0000000000000000000000000000000000000000000000;
char[61 ]  <=  640'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000380000002000000000000000000000000000000000000000000000000000000;
char[ 62]  <=  640'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
char[63 ]  <=  640'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;

  end

  always@( posedge pixel_clk or negedge sys_rst_n)
  begin
    if( sys_rst_n == 0)
    begin
      pixel_data_w <=BACK_COLOR ;
    end
else if((pixel_xpos_w >= CHAR_X_START) && (pixel_xpos_w < CHAR_X_START + CHAR_WIDTH)
         && (pixel_ypos_w >= CHAR_Y_START) && (pixel_ypos_w < CHAR_Y_START + CHAR_HEIGHT)) begin
        if(char[y_cnt][CHAR_WIDTH -1'b1 - x_cnt])
            pixel_data_w <= CHAR_COLOR;    //显示字符
        else
            pixel_data_w <= BACK_COLOR;    //显示字符区域的背景色
    end
    else
        pixel_data_w <= BACK_COLOR;        //屏幕背景�?
end
 

endmodule

video_driver.v

module video_driver
(
  input                         pixel_clk    ,
  input                         rst_n        ,
  input        [ 23 : 0 ]       pixel_data   ,

  output       [ 23 : 0 ]       video_rgb    ,
  output                        video_hs     ,     //  行同步信号
  output                        video_vs     ,     //  场同步信号
  output                        video_de     ,     //  数据使能
  output       [ 11 : 0 ]       pixel_xpos   ,     //  像素点横坐标  1280
  output       [ 11 : 0 ]       pixel_ypos        //  像素点横坐标  720
);

  //parameter define

  //1280*720  分辨率时序参数    时钟频率74.25
  parameter  H_SYNC   =  12'd40;   //行同步
  parameter  H_BACK   =  12'd220;  //行显示后沿
  parameter  H_DISP   =  12'd1280; //行有效数据
  parameter  H_FRONT  =  12'd110;  //行显示前沿
  parameter  H_TOTAL  =  12'd1650; //行扫描周期

  parameter  V_SYNC   =  12'd5;    //场同步
  parameter  V_BACK   =  12'd20;   //场显示后沿
  parameter  V_DISP   =  12'd720;  //场有效数据
  parameter  V_FRONT  =  12'd5;    //场显示前沿
  parameter  V_TOTAL  =  12'd750;  //场扫描周期



  //  reg define
  reg [11 : 0]   cnt_h ;
  reg [11 : 0]   cnt_v ;

 wire data_reg ; 
  // define








  //  next is main code
  always@(posedge pixel_clk or negedge rst_n)
  begin
    if( rst_n == 0)
    begin
      cnt_h <= 0 ;
    end
    else
    begin
      if(cnt_h == H_TOTAL - 1)
      begin
        cnt_h <= 0 ;
      end
      else
        cnt_h <= cnt_h + 1 ;
    end
  end


  always@(posedge pixel_clk or negedge rst_n)
  begin
    if( rst_n == 0)
    begin
      cnt_v = 0 ;
    end
    else
    begin
      if( cnt_h == H_TOTAL - 1)
      begin
        if(cnt_v == V_TOTAL - 1)
        begin
          cnt_v <= 0 ;
        end
        else
        begin
          cnt_v <= cnt_v + 1 ;
        end
      end
    end
  end



//    =======================main code============\\
 // video_rgb 
 // video_hs  
 // video_vs  
 // video_de  
 // pixel_xpos
 // pixel_ypos 
assign video_hs = 1 ; 
assign video_vs = 1 ; 

assign video_rgb  =   video_de ? pixel_data : 24'b0 ; 

assign video_de   =  (((cnt_h >= H_SYNC+H_BACK) && (cnt_h < H_SYNC+H_BACK+H_DISP))
&&((cnt_v >= V_SYNC+V_BACK) && (cnt_v < V_SYNC+V_BACK+V_DISP)))
?  1'b1 : 1'b0;

assign data_reg   =  (((cnt_h >= H_SYNC+H_BACK - 1) && (cnt_h < H_SYNC+H_BACK+H_DISP - 1))
&&((cnt_v >= V_SYNC+V_BACK) && (cnt_v < V_SYNC+V_BACK+V_DISP)))
?  1'b1 : 1'b0;

assign pixel_xpos = data_reg ? (cnt_h - (H_SYNC + H_BACK - 1'b1)) : 0;
assign pixel_ypos = data_reg ? (cnt_v - (V_SYNC + V_BACK - 1'b1)) : 0;

endmodule
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