HDLBits刷题（电路-组合逻辑-基本门）

wire

module top_module (
    input in,
    output out);
assign out=in;
endmodule

GND

module top_module (
    output out);
assign out=1'b0;
endmodule

NOR

module top_module (
    input in1,
    input in2,
    output out);
    nor n1(out,in1,in2);
endmodule

Another gate

module top_module (
    input in1,
    input in2,
    output out);
    assign out=in1&(!in2);
endmodule

Two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    assign out=in3^!(in1^in2);
endmodule

More logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    and a1(out_and,a,b);
    or  a2(out_or,a,b);
    xor  a3(out_xor,a,b);
    nand a4(out_nand,a,b);
    nor  a5(out_nor,a,b);
    xnor  a6(out_xnor,a,b);
    and  a7(out_anotb,a,!b);
endmodule

7420 chip

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y=!(p1a&p1b&p1c&p1d);
    assign p2y=!(p2a&p2b&p2c&p2d);
endmodule

Truth tables(真值表)

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f=(!x3&x2&!x1)||(!x3&x2&x1)||(x3&!x2&x1)||(x3&x2&x1);
endmodule

Two bits equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z= (A==B) ? 1'b1 : 1'b0;
endmodule

simple circuit A

module top_module (input x, input y, output z);
    assign z = (x^y) & x;
endmodule

simple circuit B

module top_module ( input x, input y, output z );
    assign z=!(x^y);
endmodule

combine circuit A and B

module top_module (input x, input y, output z);
    wire z1,z2,z3,z4;
    assign z1 = (x^y) & x;  assign z3 = (x^y) & x;
    assign z2=!(x^y);		assign z4=!(x^y);
    assign z=(z1|z2)^(z3&z4);
endmodule

Ring or vibrate

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer= (!vibrate_mode)?ring:1'b0;
    assign motor= (vibrate_mode)?ring:1'b0;
endmodule

Thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    assign heater= (mode==1'b1)?too_cold :1'b0 ;
    assign aircon= (mode==1'b0)?too_hot :1'b0 ;
    assign fan=((mode==1'b1)?too_cold :1'b0)||((mode==1'b0)?too_hot :1'b0)||fan_on;
endmodule

3-bit population counts

module top_module( 
    input [2:0] in,
    output [1:0] out );
    assign out=in[0]+in[1]+in[2];
endmodule

Gates and vectors

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_both=in[2:0]&in[3:1];
    assign out_any=in[3:1]|in[2:0];
    assign out_different=in[3:0]^{in[0],in[3:1]};
endmodule

Even longer vectors

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    integer i;
    assign out_both=in[98:0]&in[99:1];
    assign out_any=in[99:1]|in[98:0];
    assign out_different=in[99:0]^{in[0],in[99:1]};
endmodule