verilog入门 之 秒计数器

module s_counter(
	clk,
	res,
	s_sum
);

	input clk,res;
	output[3:0] s_sum;
	reg[3:0] s_sum;

	parameter frequency=24;//定义参数：频率24hz
	reg[24:0] con_t; //计数器

	reg s_pluse;//秒脉冲
	
	//@当时钟信号或者复位信号到来，出发该always
	always@(posedge clk or negedge res) begin
		if(~res) begin//复位信号出发，对变量进行复位
			con_t<=0;
			s_pluse<=0;
			s_sum<=0;
		end
		else begin
			//对con_t进行计数，直到con_t=24000000
			if(con_t==frequency*1000000-1) begin
				con_t<=0;
			end
			else begin
				con_t<=con_t+1;
			end

			//每当con_t计数完成一个循环，就输出一个秒脉冲，即s_pluse<=1;
			if(con_t==0) begin
				s_pluse<=1;
			end
			else begin
				s_pluse<=0;
			end
			
			//对秒数进行计数，最大计数到9
			if(s_pluse) begin
				if(s_sum==9) begin
					s_sum<=0;
				end
				else begin
					s_sum<=s_sum+1;
				end

			end
			else begin
				s_sum<=s_sum;
			end

		end
	end

endmodule

//编写测试平台
module s_counter_tb;

	reg clk,res;
	wire[3:0] s_sum;


	s_counter s_counter(
		.clk(clk),
		.res(res),
		.s_sum(s_sum)
	);


	initial begin
		clk<=0;res<=0;
		#17 res<=1;
		#100000 $stop;
	end

	always #5 clk<=~clk;//时钟

endmodule