基于TI的TDA4高速信号仿真条件的理解 4.4

Application Note
《Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines》

4.4 Time Domain Reflectometry (TDR) Analysis 时域反射计分析

As a lot of the design fixes are targeted towards maintaining uniform trace impedance, an important analysis method used in assessing the quality of the design is the Time Domain Reflectometry (TDR) Analysis.

由于许多设计修复的目标是保持均匀的走线阻抗，因此用于评估设计质量的重要分析方法是时
域反射（TDR）分析。

This plots he impedance of a trace as a function of its length. An example of this is shown in Figure 4-1.
这是将线路的阻抗绘制成其长度的函数。如图4-1所示。

Figure 4-1. TDR Plot Example With Impedance Mismatch阻抗不匹配的tdr图示例

As shown in Figure 4-1 (TDR plot example), the TDR plot highlights impedance discontinuities in the trace from one end to the other.

如图4-1所示（TDR图示例），TDR图突出了从一端到另一端走线中的阻抗不连续。

This method depends on a reflected waveform from the far-end of the trace.

这种方法依赖于来自轨迹远端的反射波形。

The delay in the plot corresponding to a particular point in the trace actually corresponds to 2 times the distance of that point from the source, owing to the round trip time.

由于往返时间，图中对应于轨迹中特定点的延时实际上对应于2 乘以该点到源的距离。

This needs to be factored in for assessing the source of impedance discontinuities.

在评估阻抗不连续的来源时，需要考虑到这一点

The TDR plot can be generated by reading in the S-parameter models generated by the extraction tool and assessing them in “Time-Domain” mode.

通过读取提取工具生成的s参数模型，并在“时域”模式下对其进行评估，可以生成TDR图。

A standard EDA simulator such as HyperLynx can perform this function.

标准的EDA模拟器（如HyperLynx）可以执行此功能。

It is recommended to optimize the design to within a ± 5% deviation from the nominal trace impedance.
建议优化设计，使其与标称走线阻抗的偏差在土5%以内。