Unity Learning for Day 17

本文介绍如何在Unity3D中实现RPG游戏剧情系统。通过系统分层与协程,实现基于命令的剧情配置,并利用类似电影剧本的方式描述剧情流程。同时,讨论了如何设定触发条件来启动特定剧情。

1、游戏程序

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2、游戏策划

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3、游戏美术

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4、Unity3D如何实现RPG游戏中的剧情?

如果你可以认同代码即数据,c#就是一个不错的脚本语言两个观点的话,请往下看:
首先需要明确剧情系统的目标:
剧情所要解决的核心问题就是:
如何调度不同的系统来处理分布在时间轴上面的剧情命令;
核心解决思路就是两个:
系统分层和协程。

如同拍摄电影一样,制作RPG游戏的剧情需要有不同的系统协作:
最重要的是导演,负责调度控制剧情流程,而剧情的具体流程类似于剧本,电影工业中剧本的书写方法是:
首先确定拍摄的环境地点,人物
接着一行,一行描述,对话,镜头,人物的相关行为;
我们的目标就是,将剧情的配置方式完全参考电影剧本来做,采用命令模式描述就是:
场景 10006 野外1;
创建玩家在 100 100点上;
创建怪物在 110 110点上;
UI展示剧情对话1,玩家头像,内容 你好呀;
UI展示剧情对话2,怪物头像,内容 天气真好;
玩家对象 发动攻击;
延迟1s;
创建攻击粒子;
拉近尽头到玩家手上;

要实现上面这种基于命令的配置方式,需要实现以下内容:
系统分层:
对话,UI,镜头控制,角色控制等是游戏中的不同系统,这些不同系统对外提供一些接口,用于实现对剧情展示的支持;
导演剧本:
针对每个剧情书写特定的剧本,可以设计一种 领域特定语言,来编写类似于与上面的剧情命令脚本;
开发量更小的方法,使用unity自带的协程来书写,类似于这样:
IEnumerator StoryProgress()
yield return StartCoroutine(CreatePlayer());
yield return StartCoroutine(CreateMonster()):
yield return StartCoroutine(ShowUI(“Hello world”));
yield return StartCoroutine(WaitForEvent(“MonsterDie”));
}
这样一个导演剧本是独立于所有系统的,只负责组织和操控其它系统;
通过协程我们可以实现,等待特定事件,等待某个操作结束,等待一定时间,而这3个能力,就可以实现一个优雅的线性的剧情描述了。
而只需要在合适的时候,执行上面的 StoryProgress,就可以做到通过特定的事件来触发特定的剧情。
当然你需要注意一点,在播放剧情之前,可能需要对当前游戏环境进行清理,例如网络游戏中,隐藏其它玩家,隐藏其它不相关怪物,等等。
而要开发相关的剧情编辑器的功能就是,将编辑好的时间轴生成相关的StoryProgress的c#代码即可。
至此一个优雅的剧情系统就完成了。
一个简单参考实现:
http://my.oschina.net/u/186074/blog/528266
当然上面描述了这些,只解决了一个底层问题,即如何组织一个剧情故事;
而上层问题是,如何设定在合适的条件下,触发某个剧情,设计思路如下,首先设定某个剧情,在满足哪些条件的情况下触发;
例如:满足和Npc1对话过,和Npc2对话过,要和Npc3对话,背包里面有物品item1;
而剧情触发经常是在处理要和Npc3对话时,对条件进行检测;
因此需要在系统中存系统的条件变量,例如主线任务进行到某一步的条件变量;
当和某个NPC对话时,触发剧情检测,若条件变量满足,则触发剧情。
因此需要设计:主动触发剧情检测的观察点,系统的条件变量,以及 满足哪些条件触发某个剧情相关配置。举几个检测点的例子:
1:在和某NPC对话时检测剧情条件是否成立;
2:在进入场景的时候检测剧情条件是否成立;
3:在进入某个区域时检测剧情条件是否成立;

游戏程序知识地图:

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### Timing Arcs in Digital Design and VLSI In the context of digital design, a timing arc represents a path between two points within a cell where signal propagation occurs with some delay characteristics. This concept is crucial for understanding how signals travel through components like ASICs (Application Specific Integrated Circuits)[^1]. Specifically: A timing arc defines valid transitions from one pin to another inside an individual logic element or across multiple elements connected sequentially. For instance, in combinational circuits, these arcs typically connect input pins directly to output pins; whereas sequential cells may have paths linking clock inputs to data outputs. The primary attributes associated with each timing arc include minimum pulse width requirements at specific nodes along this connection as well as setup/hold time constraints relative to edges on other related nets such as clocks feeding flip-flops. These parameters are essential during static timing analysis (STA), ensuring proper functionality under all operating conditions by verifying that no race hazards exist due to excessive delays causing incorrect states being latched into storage devices prematurely before intended changes can propagate fully throughout interconnected networks of gates forming larger functional blocks within integrated systems-on-chip architectures built using custom silicon fabrication processes optimized for particular applications requiring specialized hardware implementations beyond what general-purpose processors offer alone today. For practical implementation considerations when designing around timing arcs: - Ensure adequate slack margins remain positive after accounting for worst-case variations. - Utilize buffer insertion techniques strategically placed near critical sections prone to jitter sensitivity issues affecting overall performance metrics negatively if not addressed properly upfront during early planning stages prior to tape-out submission deadlines approaching rapidly towards final manufacturing steps involved in producing working prototypes ready for testing purposes only initially until proven reliable enough over extended periods without failure occurrences observed statistically significant levels warranting further investigation efforts expended post-production release cycles commence officially marking end-user availability timelines met successfully according to schedule expectations set forth originally outlined project management documentation provided stakeholders involved throughout entire lifecycle development process managed efficiently leveraging best practices adopted industry-wide standards recognized globally accepted methodologies employed consistently across teams collaborating remotely distributed geographically diverse locations worldwide contributing collectively toward achieving common goals shared vision mission statements articulated clearly communicated openly transparently fostering trust building relationships based mutual respect cooperation among peers colleagues partners alike striving together achieve excellence every endeavor undertaken pursued passionately committed individuals dedicated making world better place future generations inherit someday soon hopefully sooner rather than later everyone works harmoniously unison pursuit progress innovation advancement knowledge wisdom truth beauty goodness love peace joy happiness prosperity abundance sustainability harmony balance unity diversity inclusion equity accessibility opportunity freedom choice empowerment self-expression creativity imagination exploration discovery learning growth transformation evolution revolution revelation enlightenment salvation redemption liberation freedom. ```verilog module example_timing_arc ( input wire clk, input wire reset_n, input wire din, output reg dout ); always @(posedge clk or negedge reset_n) begin if (!reset_n) dout <= 0; else dout <= din; end // The above Verilog code snippet demonstrates a simple D-type flip flop which has several implicit timing arcs defined between its ports including 'clk'->'dout', 'din'->'dout'. ```
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