FPGA编译流程中Analysis，Elaboration，Synthesis之间的区别

最新推荐文章于 2025-05-20 13:01:00 发布

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最新推荐文章于 2025-05-20 13:01:00 发布

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本文详细介绍了FPGA设计过程中的三个关键步骤：分析、综合与布局布线前的准备（即细化）。首先，分析阶段检查设计文件的语法与语义错误；接着，在细化阶段建立设计的层次结构；最后，综合阶段将高层次的设计映射到具体的门级组件。

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Do you recognize that feeling when you think you knew something, until somebody asks you to explain it?

Well, that was what happened to me when I tried to explain what "Analysis and Elaboration" is. I used it in FPGA tools many times, and I had a certain "knowledge" of what it was, but, what are those processes EXACTLY? And, while we are at it, we will also describe what Synthesis is.

Let's see:

Analysis

Analysis is the process where the design files are checked for syntactic and semantic errors. The syntactic rules are dictated by the language. On VHDL, if you write IF but forget to include the THEN clause, that is a violation of the syntax, the set of rules of the VHDL language.

Semantics are the meaning of the language. A sentence describing an addition is tagged as incorrect if the operands are of incompatible types and the VHDL compiler cannot resolve the meaning of that sentence.

Elaboration

VHDL designs are hierarchic by nature. The top entity instantiates signals, components and processes. Each component instantiates additional signals, components and processes. The compiler explores the top-down design hierarchy and builds an interconnection table until it reaches the building blocks of the design. At this step the building blocks are still generic RTL constructs: Logic gates, registers, memories, etc.

Synthesis

During Synthesis, the design is mapped from RTL generic constructs to gate-level components. On an FPGA the building blocks are the device primitives: LUTs, flip-flops, memories, PLLs, input-output pins, etc.

http://fpgasite.blogspot.com/2017/04/analysis-elaboration-and-syntesis.html