记录Verilog编译错误（10200），未解决

出错背景

实验：右移移位寄存器

Verilog源码：

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
); 

/** The input port is replaced with an internal signal **/
wire reset = PB[0];
wire clk   = PB[1];
wire Load  =S[8];
wire [7:0] In=S[7:0];
wire Enable=S[9];
/************* The logic of this experiment *************/
logic [7:0]q;
localparam N = 8;

RightShifter #(N) R0(.Clk(clk),.Reset(reset),.iLoad(Load),
.iEnable(Enable),.iD(In),.oQ(q),.iShiftIn(q[0]));

always @(posedge clk or posedge reset)
	if(Load)
		q <= In;
	else if(reset)
		q <= 1;
	else 
		q <= {q[6:0], q[7]};

/****** Internal signal assignment to output port *******/
assign L[7:0] = q[7:0];

endmodule


module RightShifter
#(parameter N=4)
(
	input logic Clk,
	input logic Reset,
	input logic iLoad,
	input logic iEnable,
	input logic iShiftIn,
	input logic [N-1:0] iD,
	output logic [N-1:0] oQ
);
always @(posedge Clk or posedge Reset)
	if(Reset)
		oQ<=1;
	else if(iLoad)
		oQ<=iD[N-1:0];
	else if(iEnable)
		oQ<={oQ[0],oQ[N-1:1]}; 
		
endmodule

编译结果：

开始编译
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
    Info: Copyright (C) 2021  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and any partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details, at
    Info: https://fpgasoftware.intel.com/eula.
    Info: Processing started: Wed Mar 23 23:57:49 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab -c Lab
Info (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /home/519521/intelFPGA_lite/21.1/quartus/linux64/assignment_defaults.qdf
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file LabBoard_TOP.v
    Info (12023): Found entity 1: LabBoard_TOP File: /home/lems/new/compile/3191801018/projects/LabProject_1645346714386/LabBoard_TOP.v Line: 2
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
    Info (12023): Found entity 1: pll File: /home/lems/new/compile/3191801018/projects/LabProject_1645346714386/pll.v Line: 40
Info (12021): Found 2 design units, including 2 entities, in source file GlobalCLK.v
    Info (12023): Found entity 1: GlobalCLK_altclkctrl_7ji File: /home/lems/new/compile/3191801018/projects/LabProject_1645346714386/GlobalCLK.v Line: 46
    Info (12023): Found entity 2: GlobalCLK File: /home/lems/new/compile/3191801018/projects/LabProject_1645346714386/GlobalCLK.v Line: 97
Info (12021): Found 1 design units, including 1 entities, in source file JutagScanChain.qxp
    Info (12023): Found entity 1: JutagScanChain File: /home/lems/new/compile/3191801018/projects/LabProject_1645346714386/JutagScanChain.qxp Line: -1
Info (12127): Elaborating entity "LabBoard_TOP" for the top level hierarchy
Info (12128): Elaborating entity "pll"