YTM32的Flash控制器EFM模块详解

本文详细介绍了YTM32系列MCU的嵌入式Flash模块EFM,涵盖了Flash存储器特性、操作流程、约定术语、地址空间以及高级功能如BootSwap操作、调试端口和地址保护。

YTM32的Flash控制器EFM模块详解

Flash存储器控制器EFM模块概述

Flash(闪存)是一种可擦除的只读存储器,按照实现方式和运行特性Flash一般还会分为NORNAND两种。其中NOR Flash支持随机地址的读取方式,在读取操作上类似于RAM,比较适合程序的直接读取运行,而NAND Flash读取是基于页的方式,一般无法随机读取。在微控制器中,Flash需要存储程序和数据,所以大多使用NOR Flash

YTM32的Flash存储器特性

YTM32系列MCU中通过Flash控制器EFM(Embedded Flash Module)控制管理Flash存储器,这里以ME0x系列MCU为例,EFM模块支持如下的一些功能:

  • 512KB x 2 的程序存储区域PFlash,带有ECC功能,Sector大小为2K
  • 256KB 单独的数据存储块DFlash,带有ECC功能,Sector大小为1K
  • 4KB的NVR区域,带有ECC功能,Sector大小为1K
  • 支持Flash按区域(16KB单位)的写保护功能。YTM32的M系列设计写保护固定为32x2个区域,总Flash
  • 支持配置禁用调试器
  • 支持产生Flash命令执行结束和异常中断
  • 支持Block Swap的OTA升级功能
  • 支持ECC错误地址记录和单比特、多比特中断
  • 支持OTP(One Time Program,一次可编程)区域
  • 支持HCU 密钥存储(可擦写,不可读取)
  • 支持块擦除、扇区(Sector)擦除和整个Chip的擦除操作
  • 最小写入页大小为 8 Bytes

Flash的约定术语

这里梳理使用Flash过程中常用的一些约定术语:

  • PFlash,程序Flash,实际也可以保存数据,属于基于应用场景的一种约定名称。
  • DFlash,数据Flash,实际也可以运行程序,属于基于应用场景的一种约定名称。
  • Block,Flash块的存储映射空间,表示物理上的一个Flash块(PFlash0、PFlash1、DFlash等),不同物理块的Flash相互之间可以支持Read While Write(RWW)特性。
  • Sector,扇区,是Flash擦除的最小单位,属于Flash的物理特性,软件无法修改。
  • Page,Flash 编程的最小单位,同样属于Flash物理特性,软件无法修改。
  • RWW,Read While Write,在运行擦除或者编程Flash的操作时,同时支持读Flash的操作。
  • ECC校验,纠错算法的一种,可以纠正单比特错误,检测多比特错误。

存储器的地址空间及定义

以ME0x微控制器为例,芯片系统存储的映射地址空间,如表x所示。

表x YTM32微控制器片内存储映射空间
Flash Device Name Address Space Size(KB) Block Protect
PFlash0 0x0000_0000 - 0x0007_FFFF 512 KB 0 ADDR_PROT0
PFlash1 0x0008_0000 - 0x000F_FFFF 512 KB 1 ADDR_PROT1
DFlash 0x0010_0000 - 0x0013_FFFF 256 KB 2 ADDR_PROT2
AES_NVR / HCU_NVR 0x1000_0000 - 0x1000_03FF 1 KB 0 No Read + Customer Key
OTP_NVR 0x1001_0000 - 0x1001_03FF 1 KB 0 No Erase
BOOT_NVR 0x1002_0000 - 0x1002_03FF 1 KB 1 SWAP CMD only
### YTM32 IIC (I²C) Programming Tutorial #### Overview of I²C Configuration on YTM32B1MC0 The configuration and use of the Inter-Integrated Circuit (I²C) protocol with the YTM32B1MC0 microcontroller involve setting up specific registers to enable communication between devices over two wires: SDA (Serial Data Line) and SCL (Serial Clock Line). The setup process includes configuring clock speeds, enabling interrupts if necessary, and handling start/stop conditions as well as read/write operations. For initializing an I²C interface on a YTM32 device like the B1 series, one should refer closely to the provided demo examples which serve both demonstration purposes and detailed explanations about how each part works together[^1]. #### Key Points in Setting Up I²C Communication To establish proper I²C communication using YTM32 chips: - **Initialization**: Initialize the I²C peripheral by specifying parameters such as speed mode (standard/fast), address format, own slave address when acting as master/slave. - **Clock Control**: Adjust prescalers within the I²C module according to desired bit rates while ensuring stability under varying power supply voltages. - **Interrupt Handling**: Implement interrupt service routines that can handle events during data transfer including ACKnowledge failures, bus errors, etc., thus maintaining robustness against potential issues arising from hardware bugs similar to those reported for STM32's implementation[^2]. Here is a simplified example demonstrating initialization steps written in C language targeting GCC compiler toolchain commonly used alongside ARM Cortex-M cores found inside these MCUs: ```c #include "ytm32fxxx_hal.h" // Assume `hi2c` has been declared globally somewhere earlier... void MX_I2C_Init(I2C_HandleTypeDef* hi2c){ /* USER CODE BEGIN I2C_Init 0 */ /* USER CODE END I2C_Init 0 */ // Configure I2C settings here... } ``` This code snippet provides only placeholders where actual configurations would take place based upon application requirements. For more comprehensive guidance tailored specifically towards cloud chip products manufactured by YunTu Semiconductor Co Ltd, consulting their official reference manuals becomes essential since they contain precise instructions regarding register mappings along with other critical details pertinent to successful integration into projects involving serial communications protocols like UARTs too[^3]. #### Additional Resources Beyond direct coding practices, understanding underlying principles behind boot processes also plays a significant role especially concerning security aspects related to firmware updates via bootloader mechanisms present even at lower levels affecting higher-level functionalities indirectly through system-wide resets triggered post-update activities[^4]. Moreover, executing commands directly onto flash memory controllers could impact overall performance metrics associated with swapping out executable images stored across different regions depending upon design choices made prior to deployment phases[^5].
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