Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.
写一个多路复用和D触发的小模块
代码:
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
wire temp;
assign temp=L?r_in:q_in;
always@(posedge clk)begin
Q=temp;
end
endmodule