（电工基地笔记）Vivado出现编译错误，无法生成bit文件

最新推荐文章于 2025-06-18 10:59:13 发布

Peter_hust

最新推荐文章于 2025-06-18 10:59:13 发布

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分类专栏： Verilog FPGA 电工基地文章标签： FPGA工程 vivado verilog

本文链接：https://blog.youkuaiyun.com/qq_33929689/article/details/52255806

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本文介绍了一种常见的XDC文件配置错误——未指定I/O标准导致的警告，该问题可能会影响硬件性能及信号完整性。文章详细解释了如何通过在XDC文件中为特定端口设置I/O标准来解决这一问题。

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error：[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 15 out of 15 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: key[5:0], led[6:0], clk, pwm.

解决办法：按照错误提示，对应IO指定电压，比如我在xdc文件添加了：

set_property IOSTANDARD LVCMOS33 [get_ports clk];

......