Circuits--Sequence --FSM--q8~q5a

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#fpga开发 #笔记

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1. q8

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    
    parameter s0 = 2'd0;
    parameter s1 = 2'd1;
    parameter s2 = 2'd2;
  
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    always@(*)
        begin
            case(state)
               s0:
                   begin
                       if(x) next_state = s1;
                       else  next_state = s0;
                   end
               s1:
                   begin
                       if(x) next_state = s1;
                       else  next_state = s2;
                   end
               s2:
                   begin
                       if(x) next_state = s1;
                       else  next_state = s0;
                   end
              
           endcase
        end
    
    always@(posedge clk or negedge aresetn)
        begin
            if(~aresetn)
                state <= s0;
            else
                state <= next_state;
        end
    
    assign z = (state == s2) ? x : 1'b0;

endmodule

2. q5a

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    
    parameter s0 = 2'd0;
    parameter s1 = 2'd1;
    parameter s2 = 2'd2;
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    always@(*)
        begin
            case(state)
                s0:
                    if(x) next_state = s1;
                	else  next_state = s0;
                s1:
                    if(x) next_state = s2;
                	else  next_state = s1;
                s2:
                    if(x) next_state = s2;
                	else  next_state = s1;
            endcase
        end
    
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                state <= s0;
            else
                state <= next_state;
        end
    
    assign z = (state == s1);

endmodule