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RSS订阅原创 More Verilog Features
Conditional ternary operators三目运算符(Condition?) if_ture: if_false;题目描述：比较四位无符号数a，b，c，d的大小，注意位宽为8。module top_module ( input [7:0] a, b, c, d, output [7:0] min);// wire interm1; //运行错误原因在这儿 wire inter.
2021-12-25 22:36:03
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原创 Procedures
Always blocks(combinational)-Alwaysblock1题目描述：分别用assign连续赋值和always过程块描述 逻辑与门A note on wire vs. reg:The left-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block).
2021-12-23 22:31:39
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