Verilog中行为延迟详解：不同类型的assign与clock generation
本文详细讲解了Verilog中assign、blocking assignment和non-blocking assignment的延迟使用，以及如何在clock generation模块中设置合理的延时。重点介绍了放置延迟在LHS和RHS的区别，并提供了clock信号生成的示例。
在verilog中添加delay
推荐
- assign #5 y=~x;
- always @ (a) y <= #5 ~a;
Continuous assignment delay
assign #5 y = ~x; OK
Blocking assignment delay
always @(a) #5 y = ~a; LHS
always @(a) y = #5 ~a; RHS
placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events.
do not place delays on the RHS of blocking assignments in a testbench.
Nonblocking assignment delay
always @(a) #5 y <= ~a;
always @(a) y <= #5 ~a; 推荐的
clock generation
module top;
bit clk = 0;
always #5 clk = ~clk;
...
endmodule
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