在verilog中添加delay
推荐
- assign #5 y=~x;
- always @ (a) y <= #5 ~a;
Continuous assignment delay
assign #5 y = ~x; OK
Blocking assignment delay
always @(a) #5 y = ~a; LHS
always @(a) y = #5 ~a; RHS
placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events.
do not place delays on the RHS of blocking assignments in a testbench.
Nonblocking assignment delay
always @(a) #5 y <= ~a;
always @(a) y <= #5 ~a; 推荐的
clock generation
module top;
bit clk = 0;
always #5 clk = ~clk;
...
endmodule