producing simulation results

最新推荐文章于 2023-06-10 02:48:45 发布

原创最新推荐文章于 2023-06-10 02:48:45 发布 · 689 阅读

0 ·

CC 4.0 BY-SA版权

文章标签：

#include #output

IC验证专栏收录该内容

24 篇文章

订阅专栏

本文探讨了在Verilog中优化采样过程的方法，包括使用主动$monitor任务进行条件触发采样、减少不必要的采样操作以及利用always块实现高效采样策略。详细介绍了如何通过控制采样时机来最小化资源消耗并提高测试覆盖率。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

1. several ways to sample output signal

always @(negedge clk)
begin
   $strobe(...)
end

parameter INTERVAL = 10;
always
begin
   #(INTERVAL);
   $strobe(...);
end

always @(q, qb)
begin
   $strobe("...", rst, d0, d1, sel, q, qb);
end

initial
begin
   $monitor("...", rst, d0, d1, sel, q, qb);
end

2. Minimizing Sampling

An active $monitor task can be turned on and off by using the $monitoron and $monitoroff tasks, respectively. If you are using an explicit sampling always block, you should include sampling minimization techniques in your model, as illustrated in Sample 5-34. A very efficient way of minimizing sampling is to have the stimulus
turn on the sampling when an interesting section of the testcase is entered, as shown in Sample 5-35.

always
begin
wait (<interesting_condition>);
while (<interesting_condition>) begin
      @ (q, qb;)
      $strobe(“...”, rst, d0, d1, sel, q, qb);
   end
end

initial
begin
   $monitor("...", rst, d0, d1, sel, q, qb);
$monitoroff;
   sync_reset;
   load_d0(1);
   sync_reset;
$monitoron;
   load_d1(1);
   load_d0(0);
   load_d1(1);
   sync_reset;
$monitoroff;
   ...
end