ASIC开发流程

1.Design Specification

 The design flow begins with a written specification for the design. The specification document can be a very elaborate statement of functionality, timing ,silicon area,power consumption ,testability,fault coverage,and other criteria that govern the design. At a minimum,the specification describes the functional characteristic that are to be implemented in a design.Typically,state transition graphs,timing charts,and algorithmic-state machine(ASM)charts are

used to describe sequential machines,but interpretation of the HDL-based model might actually implement an

unintended interpretation of the specification.

 

2.Design Partition

 

3.Design Entry

 

4.simulation and Functional Verification

 

5.Design Integration and  Verification

 

6.Presynthesis Sign-off

 

7.Gate-level Synthesis and Technology Mapping

 

8.Postsynthesis Design Validation

   Design validation compares the response of the synthesized gate-level description to the response of the behavioral mdodel .This can be done by a testbench that instantialtes both models ,and drives them with a common stimulus .For synchronous design ,the match must hold at the boundries of the machine's cycle-intermediate activity is of no consequence .

 Postsynthesis design validation can reveal software race conditions(竞争条件) in the behavioral model that cause

events to occur in a different clock cycle than expected . 

 

9.Postsynthesis Timing Verification

Although the synthesis process is intended to produce a circuit thatmeets timing specifications,the circuit's timing

margin must be checked to verify that speeds are adequate on critical paths.

 

10.Test Generation and Fault Simulation

Testing considers process-induced faults,not design errors.Design errors should be detected before presynthesis sign-off. Testing is duinting,for an ASIC chip might have millinons of transisitors, but only a few hundred package pins that can be used  to probe the internal circuits . The designer might have to embed additional ,special circuits that will enable a tester to use only a few external pins to test the entire internal circuitry of the ASIC,either alone or on a printed circuit board.

 

11.Cell placement ,scan chain and clock tree insertion,cell routing

 

12.verify physical and electrical desihn rules

 

13.extrct parssitics

 

14.design  sign-off