maxzcl的博客

[1] short description: Power Delivery Network (PDN) - Semiconductor Engineering[2] PDN on PCB:Power Distribution Network in PCB Design: Ensuring Stable Power Delivery[3] lecture slides on PDN: https://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf[4] (RL

In light of NV's recent addition of fp4, I'm once again curious about the bottom line for LLM, at least for inference; let's go back to this BitNet paper from Microsoft, featuring 1 bit LLM, with 1-bit weights trained from scatch, and later on another feat

Learn how。

【代码】Direct vs Indirect Branching。

Conventional two flip-flop synchronizerfrom Synchronizer Techniques for Multi-Clock Domain SoCs & FPGAs - EDN In general, a conventional two flip-flop synchronizer is used for synchronizing a single bit level signal. As shown in Figure 1 and Figure 2 , fli

slides from https://inst.eecs.berkeley.edu/~cs150/fa05/Lectures/07-SeqLogicIIIx2.pdf==> output is not dependent on input, but next state still iswith the merging rule stated in the beginning:(starting from the Moore diagram, but change it to a Mealy first,

【代码】Initial Block and Testbenches in Verilog。

process corners

breakdown Decouple! Provide Use!

Setup and Hold Time in an FPGAWhat is Setup and Hold Time in an FPGA?Setup time and Hold time are important concepts to understand for every digital designer. This article explains what setup and hold times are and how they are used inside of an FPGA.

Passive Componentshttps://www.allaboutcircuits.com/technical-articles/schematic-symbols-electronic-components-passives-resistors-capacitors/==> a well loaded article with most passive unit electrical components and follow up links on details of the

What are the meaning of Vdd and Vss? Vcc and Vee?? GND? - Mis CircuitosIt has always been a bit intriguing and even confusing the nomenclature of these power voltages (VddandVss) or (VccandVee).The following pictures are worth a thousand words…...

all taken from WikipediaRChttps://en.wikipedia.org/wiki/RC_circuitusingKirchhoff's current lawSeries Circuithere we exploit reactance/impedance, see later in capacitor section.s is for "second", since Q = I * t, C = Q/V ==> 1/C ~ Oh...

the important one for hardware is AMBA AXI, which isArm Microcontroller Bus Architecture Advanced eXtensible Interfacesee Arm's own documentation for a controlled learning experience:Documentation – Arm Developerfor a comprehensive coverage of all

Communication ChannelAcommunication channelrefers either to a physicaltransmission mediumsuch as a wire, or to alogical connectionover amultiplexedmedium such as a radio channel intelecommunicationsandcomputer networking. A channel is used to...

for communication channel and channel interference see:https://blog.youkuaiyun.com/maxzcl/article/details/123753591Wireless Communication BriefingWireless Communication: Introduction, Types and ApplicationsWireless Communication is the fastest growing an

https://en.wikipedia.org/wiki/MinifloatIncomputing,minifloatsarefloating-pointvalues represented with very fewbits. Predictably, they are not well suited for general-purpose numerical calculations. They are used for special purposes, most often in...

Mean Time Between Failure (MTBF) and Its Importance to Device and System DesignKey Takeaways● Define Mean Time Between Failure (MTBF).● Gain a greater understanding of the importance of MTBF.● Learn how assessments like MTBF translate into bette...

Definition(of package, from wiki:https://en.wikipedia.org/wiki/Semiconductor_package)Asemiconductor packageis a metal, plastic, glass, or ceramic casing containing one or more discretesemiconductor devicesorintegrated circuits. Individual compon...

Recommended General SourcesWikiChipSemiconductor Engineering - Deep Insights For Chip Engineerschip, wafer, die, maskChips, wafers, dies, masks, and photolithographychip vs. diesometimes used interchangeably, else chip would specifically refer.

Numpy is by its design a SIMD structure, which is best examplified by the list indexing feature:python - How to filter numpy array by list of indices? - Stack Overflowfilter_indices = [1,3,5]np.array([11,13,155,22,0xff,32,56,88])[filter_indices]

IC Overviewhttps://en.wikipedia.org/wiki/Integrated_circuitDesign Overviewhttps://en.wikipedia.org/wiki/Integrated_circuit_designFabrication OverviewIC Fabrication Process - JavatpointTextbookhttp://www.ime.cas.cn/icac/learning/learning_3/201

Arm vs x86: Instruction sets, architecture, and more differences explainedAndroid is capable of running on three different types of processor architecture: Arm, Intel, and MIPS. The former is today’s ubiquitous architecture after Intel abandoned its hand

fromTen Lessons From Three Generations Shaped Google’s TPUv4iEvolution of ML DSAfor TPUv1 seeTPUv1: Single Chipped Inference DL DSA_maxzcl的博客-优快云博客for TPUv2/3 seehttps://blog.youkuaiyun.com/maxzcl/article/details/121399583for TPUv1 to TPUv2 seeTPUv...

Overviewhttps://en.wikipedia.org/wiki/Direct_memory_access#Modes_of_operationhttps://www.silabs.com/documents/public/application-notes/AN0013.pdfPerformancehttps://indico.cern.ch/event/453673/contributions/1951556/attachments/1170310/1689185/DMA_pe

The Design Process for Google’s Training Chips: TPUv2 and TPUv3break down of the accompanying paper:https://blog.youkuaiyun.com/maxzcl/article/details/121399583Challengesof ML Training DSAInference to TrainingMore computationMore means both the types..

unit isInference vs. TrainingBoth sharesome computational elements including matrix multiplications, convolutions, and activation functions, so inference and training DSAs might have similar functional units. Key architectural aspects where the requi.

from Will HBM replace DDR and become Computer Memory? - Utmelconclusionmain comparison==> 3d stacking structure is the main reason why HBM can give higher bandwidthHBM is the preferred DRAM NN-DSAOther AriticlesChoosing between D..