HDLbits Exams/ece241 2014 q7b

最新推荐文章于 2025-03-25 13:09:25 发布

原创最新推荐文章于 2025-03-25 13:09:25 发布 · 351 阅读

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这篇文章介绍了如何从1000Hz时钟信号中创建一个稳定的1Hz信号，通过使用模10 BCD计数器进行分频，并详细说明了如何配置多级计数器以确保每秒仅触发一次。关键步骤包括计数器的设置和使能信号的同步输出。

原题目

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q
);

BCD counter

4位计数器，实现0-9的计数；

module BCD_counter(Clk,Cin,Rst_n,Cout,q);
 
	input Clk;    //计数基准时钟
	input Cin;    //计数器进位输入
	input Rst_n;    //系统复位
	
	output reg Cout;    //计数进位输出
	output [3:0] q;    //计数值输出

	reg [3:0] cnt;    //定义计数器寄存器
	
//执行计数过程
	always @(posedge Clk or negedge Rst_n)
	begin 
		if(Rst_n == 1'b0)
			cnt <= 4'd0;
		else if (Cin == 1'b1)
		begin
			if(cnt == 4'd9)
			cnt <= 4'd0;
			else 
			cnt <= cnt + 1'b1;
		end
		else 
			cnt <= cnt;
	end 
	
//产生进位输出信号
	always @(posedge Clk or negedge Rst_n)
	begin 
		if(Rst_n == 1'b0)
		Cout <= 1'b0;
		else if(Cin == 1'b1 && cnt == 4'd9)
		Cout <= 1'b1;
		else 
		Cout <= 1'b0;
	end
	
	assign q = cnt;
 
 
endmodule

解决方法

通过例化一个10进制bcd码计数器，来实现1000分频的分频器。

也就是说时钟是1Khz的时钟，如何通过计数得到一个1Hz的信号，持续一个时钟就行。

那就计数到999给一个输出作为1Hz信号输出。

如何实现计数到999呢？

由于给的是一个模10计数器，所以先例化一个个位计数器，计数到9，给十位计数器一个使能，让其计数，同理，十位计数器计数到9给百位计数器一个使能，就可以得到这样的一个计数器。

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); 
    wire [3:0] one,ten,hundred;
    assign c_enable = {(ten == 4'd9)&&(one == 4'd9),one == 4'd9,1'b1};
    assign OneHertz = {(hundred == 4'd9)&&(ten == 4'd9)&&(one == 4'd9)};

    bcdcount counter0 (clk, reset, c_enable[0],one);
    bcdcount counter1 (clk, reset, c_enable[1],ten);
    bcdcount counter2 (clk, reset, c_enable[2],hundred);

endmodule

原文链接：https://blog.youkuaiyun.com/Reborn_Lee/article/details/103230795