/*
* linux/arch/arm/kernel/head.S
*
* Copyright (C) 1994-2002 Russell King
* Copyright (c) 2003 ARM Limited
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Pu
blic License versi
on 2 as
* pu
blished by the Free Software Foundati
on.
*
* Kernel startup code for all 32-bit CPUs
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assem
bler.h>
#include <asm/cp15.h>
#include <asm/domain.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <asm/memory.h>
#include <asm/thread_info.h>
#include <asm/pgta
ble.h>
#if defined(C
ONFIG_DEBUG_LL) && !defined(C
ONFIG_DEBUG_SEMIHOSTING)
#include C
ONFIG_DEBUG_LL_INCLUDE
#endif
/*
* swapper_pg_dir is the virtual address of the initial page ta
ble.
* We place the page ta
bles 16K below KERNEL_RAM_VADDR. Therefore, we must
* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
* the least significant 16 bits to be 0x8000, but we could proba
bly
* relax this restricti
on to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
*/
#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
#error KERNEL_RAM_VADDR must start at 0xXXXX8000
#endif
#ifdef C
ONFIG_ARM_LPAE
/* LPAE requires an additi
onal page for the PGD */
#define PG_DIR_SIZE 0x5000
#define PMD_ORDER 3
#else
#define PG_DIR_SIZE 0x4000
#define PMD_ORDER 2
#endif
.glo
bl swapper_pg_dir
.equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
.macro pgt
bl, rd, phys
add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
.endm
/*
* Kernel startup entry point.
* ---------------------------
*
* This is normally called from the decompressor code. The requirements
* are: MMU = off, D-
cache = off, I-
cache = d
ont care, r0 = 0,
* r1 = machine nr, r2 = atags or dtb pointer.
*
* This code is mostly positi
on independent, so if you link the kernel at
* 0xc0008000, you call this at __pa(0xc0008000).
*
* See linux/arch/arm/tools/mach-types for the complete list of machine
* numbers for r1.
*
* We're trying to keep crap to a minimum; DO NOT add any machine specific
* crap here - that's what the boot loader (or in extreme, well justified
* circumstances, zImage) is for.
*/
.arm
__HEAD
ENTRY(stext)
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
#ifdef C
ONFIG_ARM_VIRT_EXT
bl __hyp_stub_install
#endif
@ ensure svc mode and all interrupts masked
safe_svcmode_maskall r9
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
movs r10, r5 @ invalid processor (r5=0)?
THUMB( it eq ) @ force fixup-a
ble l
ong branch encoding
beq __error_p @ yes, error 'p'
#ifdef C
ONFIG_ARM_LPAE
mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
and r3, r3, #0xf @ extract VMSA support
cmp r3, #5 @ l
ong-descriptor translati
on ta
ble format?
THUMB( it lo ) @ force fixup-a
ble l
ong branch encoding
blo __error_p @
only classic page ta
ble format
#endif
#ifndef C
ONFIG_XIP_KERNEL
adr r3, 2f
ldmia r3, {r4, r8}
sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
add r8, r8, r4 @ PHYS_OFFSET
#else
ldr r8, =PHYS_OFFSET @ always c
onstant in this case
#endif
/*
* r1 = machine no, r2 = atags or dtb,
* r8 = phys_offset, r9 = cpuid, r10 = procinfo
*/
bl __vet_atags
#ifdef C
ONFIG_SMP_
ON_UP
bl __fixup_smp
#endif
#ifdef C
ONFIG_ARM_PATCH_PHYS_VIRT
bl __fixup_pv_ta
ble
#endif
bl __create_page_ta
bles
/*
* The following calls CPU specific code in a positi
on independent
* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
* xxx_proc_info structure selected by __lookup_processor_type
* above.
On return, the CPU will be ready for the MMU to be
* turned
on, and r0 will hold the CPU c
ontrol register value.
*/
ldr r13, =__mmap_switched @ address to jump to after
@ mmu has been ena
bled
adr lr, BSYM(1f) @ return (PIC) address
mov r8, r4 @ set TTBR1 to swapper_pg_dir
ARM( add pc, r10, #PROCINFO_INITFUNC )
THUMB( add r12, r10, #PROCINFO_INITFUNC )
THUMB( mov pc, r12 )
1: b __ena
ble_mmu
ENDPROC(stext)
.ltorg
#ifndef C
ONFIG_XIP_KERNEL
2: .l
ong .
.l
ong PAGE_OFFSET
#endif
/*
* Setup the initial page ta
bles. We
only setup the barest
* amount which are required to get the kernel running, which
* generally means mapping in the kernel code.
*
* r8 = phys_offset, r9 = cpuid, r10 = procinfo
*
* Returns:
* r0, r3, r5-r7 corrupted
* r4 = physical page ta
ble address
*/
__create_page_ta
bles:
pgt
bl r4, r8 @ page ta
ble address
/*
* Clear the swapper page ta
ble
*/
mov r0, r4
mov r3, #0
add r6, r0, #PG_DIR_SIZE
1: str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
teq r0, r6
bne 1b
#ifdef C
ONFIG_ARM_LPAE
/*
* Build the PGD ta
ble (first level) to point to the PMD ta
ble. A PGD
* entry is 64-bit wide.
*/
mov r0, r4
add r3, r4, #0x1000 @ first PMD ta
ble address
orr r3, r3, #3 @ PGD
block type
mov r6, #4 @ PTRS_PER_PGD
mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
1:
#ifdef C
ONFIG_CPU_ENDIAN_BE8
str r7, [r0], #4 @ set top PGD entry bits
str r3, [r0], #4 @ set bottom PGD entry bits
#else
str r3, [r0], #4 @ set bottom PGD entry bits
str r7, [r0], #4 @ set top PGD entry bits
#endif
add r3, r3, #0x1000 @ next PMD ta
ble
subs r6, r6, #1
bne 1b
add r4, r4, #0x1000 @ point to the PMD ta
bles
#ifdef C
ONFIG_CPU_ENDIAN_BE8
add r4, r4, #4 @ we
only write the bottom word
#endif
#endif
ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
/*
* Create identity mapping to cater for __ena
ble_mmu.
* This identity mapping will be removed by paging_init().
*/
adr r0, __turn_mmu_
on_loc
ldmia r0, {r3, r5, r6}
sub r0, r0, r3 @ virt->phys offset
add r5, r5, r0 @ phys __turn_mmu_
on
add r6, r6, r0 @ phys __turn_mmu_
on_end
mov r5, r5, lsr #SECTI
ON_SHIFT
mov r6, r6, lsr #SECTI
ON_SHIFT
1: orr r3, r7, r5, lsl #SECTI
ON_SHIFT @ flags + kernel base
str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
cmp r5, r6
addlo r5, r5, #1 @ next secti
on
blo 1b
/*
* Map our RAM from the start to the end of the kernel .bss secti
on.
*/
add r0, r4, #PAGE_OFFSET >> (SECTI
ON_SHIFT - PMD_ORDER)
ldr r6, =(_end - 1)
orr r3, r8, r7
add r6, r4, r6, lsr #(SECTI
ON_SHIFT - PMD_ORDER)
1: str r3, [r0], #1 << PMD_ORDER
add r3, r3, #1 << SECTI
ON_SHIFT
cmp r0, r6
bls 1b
#ifdef C
ONFIG_XIP_KERNEL
/*
* Map the kernel image separately as it is not located in RAM.
*/
#define XIP_START XIP_VIRT_ADDR(C
ONFIG_XIP_PHYS_ADDR)
mov r3, pc
mov r3, r3, lsr #SECTI
ON_SHIFT
orr r3, r7, r3, lsl #SECTI
ON_SHIFT
add r0, r4, #(XIP_START & 0xff000000) >> (SECTI
ON_SHIFT - PMD_ORDER)
str r3, [r0, #((XIP_START & 0x00f00000) >> SECTI
ON_SHIFT) << PMD_ORDER]!
ldr r6, =(_edata_loc - 1)
add r0, r0, #1 << PMD_ORDER
add r6, r4, r6, lsr #(SECTI
ON_SHIFT - PMD_ORDER)
1: cmp r0, r6
add r3, r3, #1 << SECTI
ON_SHIFT
strls r3, [r0], #1 << PMD_ORDER
bls 1b
#endif
/*
* Then map boot params address in r2 if specified.
* We map 2 secti
ons in case the ATAGs/DTB crosses a secti
on boundary.
*/
mov r0, r2, lsr #SECTI
ON_SHIFT
movs r0, r0, lsl #SECTI
ON_SHIFT
subne r3, r0, r8
addne r3, r3, #PAGE_OFFSET
addne r3, r4, r3, lsr #(SECTI
ON_SHIFT - PMD_ORDER)
orrne r6, r7, r0
strne r6, [r3], #1 << PMD_ORDER
addne r6, r6, #1 << SECTI
ON_SHIFT
strne r6, [r3]
#if defined(C
ONFIG_ARM_LPAE) && defined(C
ONFIG_CPU_ENDIAN_BE8)
sub r4, r4, #4 @ Fixup page ta
ble pointer
@ for 64-bit descriptors
#endif
#ifdef C
ONFIG_DEBUG_LL
#if !defined(C
ONFIG_DEBUG_ICEDCC) && !defined(C
ONFIG_DEBUG_SEMIHOSTING)
/*
* Map in IO space for serial debugging.
* This allows debug messages to be output
* via a serial c
onsole before paging_init.
*/
addruart r7, r3, r0
mov r3, r3, lsr #SECTI
ON_SHIFT
mov r3, r3, lsl #PMD_ORDER
add r0, r4, r3
mov r3, r7, lsr #SECTI
ON_SHIFT
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
orr r3, r7, r3, lsl #SECTI
ON_SHIFT
#ifdef C
ONFIG_ARM_LPAE
mov r7, #1 << (54 - 32) @ XN
#ifdef C
ONFIG_CPU_ENDIAN_BE8
str r7, [r0], #4
str r3, [r0], #4
#else
str r3, [r0], #4
str r7, [r0], #4
#endif
#else
orr r3, r3, #PMD_SECT_XN
str r3, [r0], #4
#endif
#else /* C
ONFIG_DEBUG_ICEDCC || C
ONFIG_DEBUG_SEMIHOSTING */
/* we d
on't need any serial debugging mappings */
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
#endif
#if defined(C
ONFIG_ARCH_NETWINDER) || defined(C
ONFIG_ARCH_CATS)
/*
* If we're using the NetWinder or CATS, we also need to map
* in the 16550-type serial port for the debug messages
*/
add r0, r4, #0xff000000 >> (SECTI
ON_SHIFT - PMD_ORDER)
orr r3, r7, #0x7c000000
str r3, [r0]
#endif
#ifdef C
ONFIG_ARCH_RPC
/*
* Map in screen at 0x02000000 & SCREEN2_BASE
* Similar reas
ons here - for debug. This is
*
only for Acorn RiscPC architectures.
*/
add r0, r4, #0x02000000 >> (SECTI
ON_SHIFT - PMD_ORDER)
orr r3, r7, #0x02000000
str r3, [r0]
add r0, r4, #0xd8000000 >> (SECTI
ON_SHIFT - PMD_ORDER)
str r3, [r0]
#endif
#endif
#ifdef C
ONFIG_ARM_LPAE
sub r4, r4, #0x1000 @ point to the PGD ta
ble
#endif
mov pc, lr
ENDPROC(__create_page_ta
bles)
.ltorg
.align
__turn_mmu_
on_loc:
.l
ong .
.l
ong __turn_mmu_
on
.l
ong __turn_mmu_
on_end
#if defined(C
ONFIG_SMP)
__CPUINIT
ENTRY(sec
ondary_startup)
/*
* Comm
on entry point for sec
ondary CPUs.
*
* Ensure that we're in SVC mode, and IRQs are disa
bled. Lookup
* the processor type - there is no need to check the machine type
* as it has already been validated by the primary processor.
*/
#ifdef C
ONFIG_ARM_VIRT_EXT
bl __hyp_stub_install_sec
ondary
#endif
safe_svcmode_maskall r9
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type
movs r10, r5 @ invalid processor?
moveq r0, #'p' @ yes, error 'p'
THUMB( it eq ) @ force fixup-a
ble l
ong branch encoding
beq __error_p
/*
* Use the page ta
bles supplied from __cpu_up.
*/
adr r4, __sec
ondary_data
ldmia r4, {r5, r7, r12} @ address to jump to after
sub lr, r4, r5 @ mmu has been ena
bled
ldr r4, [r7, lr] @ get sec
ondary_data.pgdir
add r7, r7, #4
ldr r8, [r7, lr] @ get sec
ondary_data.swapper_pg_dir
adr lr, BSYM(__ena
ble_mmu) @ return address
mov r13, r12 @ __sec
ondary_switched address
ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
@ (return c
ontrol reg)
THUMB( add r12, r10, #PROCINFO_INITFUNC )
THUMB( mov pc, r12 )
ENDPROC(sec
ondary_startup)
/*
* r6 = &sec
ondary_data
*/
ENTRY(__sec
ondary_switched)
ldr sp, [r7, #4] @ get sec
ondary_data.stack
mov fp, #0
b sec
ondary_start_kernel
ENDPROC(__sec
ondary_switched)
.align
.type __sec
ondary_data, %object
__sec
ondary_data:
.l
ong .
.l
ong sec
ondary_data
.l
ong __sec
ondary_switched
#endif /* defined(C
ONFIG_SMP) */
/*
* Setup comm
on bits before finally ena
bling the MMU. Essentially
* this is just loading the page ta
ble pointer and domain access
* registers.
*
* r0 = cp#15 c
ontrol register
* r1 = machine ID
* r2 = atags or dtb pointer
* r4 = page ta
ble pointer
* r9 = processor ID
* r13 = *virtual* address to jump to up
on completi
on
*/
__ena
ble_mmu:
#if defined(C
ONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
orr r0, r0, #CR_A
#else
bic r0, r0, #CR_A
#endif
#ifdef C
ONFIG_CPU_D
CACHE_DISA
BLE
bic r0, r0, #CR_C
#endif
#ifdef C
ONFIG_CPU_BPREDICT_DISA
BLE
bic r0, r0, #CR_Z
#endif
#ifdef C
ONFIG_CPU_I
CACHE_DISA
BLE
bic r0, r0, #CR_I
#endif
#ifdef C
ONFIG_ARM_LPAE
mov r5, #0
mcrr p15, 0, r4, r5, c2 @ load TTBR0
#else
mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_TA
BLE, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r5, c3, c0, 0 @ load domain access register
mcr p15, 0, r4, c2, c0, 0 @ load page ta
ble pointer
#endif
b __turn_mmu_
on
ENDPROC(__ena
ble_mmu)
/*
* Ena
ble the MMU. This completely changes the structure of the visi
ble
* memory space. You will not be a
ble to trace executi
on through this.
* If you have an enquiry about this, *please* check the linux-arm-kernel
* mailing list archives BEFORE sending another post to the list.
*
* r0 = cp#15 c
ontrol register
* r1 = machine ID
* r2 = atags or dtb pointer
* r9 = processor ID
* r13 = *virtual* address to jump to up
on completi
on
*
* other registers depend
on the functi
on called up
on completi
on
*/
.align 5
.pushsecti
on .idmap.text, "ax"
ENTRY(__turn_mmu_
on)
mov r0, r0
instr_sync
mcr p15, 0, r0, c1, c0, 0 @ write c
ontrol reg
mrc p15, 0, r3, c0, c0, 0 @ read id reg
instr_sync
mov r3, r3
mov r3, r13
mov pc, r3
__turn_mmu_
on_end:
ENDPROC(__turn_mmu_
on)
.popsecti
on
#ifdef C
ONFIG_SMP_
ON_UP
__INIT
__fixup_smp:
and r3, r9, #0x000f0000 @ architecture versi
on
teq r3, #0x000f0000 @ CPU ID supported?
bne __fixup_smp_
on_up @ no, assume UP
bic r3, r9, #0x00ff0000
bic r3, r3, #0x0000000f @ mask 0xff00fff0
mov r4, #0x41000000
orr r4, r4, #0x0000b000
orr r4, r4, #0x00000020 @ val 0x4100b020
teq r3, r4 @ ARM 11MPCore?
moveq pc, lr @ yes, assume SMP
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
and r0, r0, #0xc0000000 @ multiprocessing extensi
ons and
teq r0, #0x80000000 @ not part of a uniprocessor system?
moveq pc, lr @ yes, assume SMP
__fixup_smp_
on_up:
adr r0, 1f
ldmia r0, {r3 - r5}
sub r3, r0, r3
add r4, r4, r3
add r5, r5, r3
b __do_fixup_smp_
on_up
ENDPROC(__fixup_smp)
.align
1: .word .
.word __smpalt_begin
.word __smpalt_end
.pushsecti
on .data
.glo
bl smp_
on_up
smp_
on_up:
ALT_SMP(.l
ong 1)
ALT_UP(.l
ong 0)
.popsecti
on
#endif
.text
__do_fixup_smp_
on_up:
cmp r4, r5
movhs pc, lr
ldmia r4!, {r0, r6}
ARM( str r6, [r0, r3] )
THUMB( add r0, r0, r3 )
#ifdef __ARMEB__
THUMB( mov r6, r6, ror #16 ) @ C
onvert word order for big-endian.
#endif
THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
THUMB( strh r6, [r0] )
b __do_fixup_smp_
on_up
ENDPROC(__do_fixup_smp_
on_up)
ENTRY(fixup_smp)
stmfd sp!, {r4 - r6, lr}
mov r4, r0
add r5, r0, r1
mov r3, #0
bl __do_fixup_smp_
on_up
ldmfd sp!, {r4 - r6, pc}
ENDPROC(fixup_smp)
#ifdef C
ONFIG_ARM_PATCH_PHYS_VIRT
/* __fixup_pv_ta
ble - patch the stub instructi
ons with the delta between
* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
* can be expressed by an immediate shifter operand. The stub instructi
on
* has a form of '(add|sub) rd, rn, #imm'.
*/
__HEAD
__fixup_pv_ta
ble:
adr r0, 1f
ldmia r0, {r3-r5, r7}
sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
add r4, r4, r3 @ adjust ta
ble start address
add r5, r5, r3 @ adjust ta
ble end address
add r7, r7, r3 @ adjust __pv_phys_offset address
str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
mov r6, r3, lsr #24 @ c
onstant for add/sub instructi
ons
teq r3, r6, lsl #24 @ must be 16MiB aligned
THUMB( it ne @ cross secti
on branch )
bne __error
str r6, [r7, #4] @ save to __pv_offset
b __fixup_a_pv_ta
ble
ENDPROC(__fixup_pv_ta
ble)
.align
1: .l
ong .
.l
ong __pv_ta
ble_begin
.l
ong __pv_ta
ble_end
2: .l
ong __pv_phys_offset
.text
__fixup_a_pv_ta
ble:
#ifdef C
ONFIG_THUMB2_KERNEL
lsls r6, #24
beq 2f
clz r7, r6
lsr r6, #24
lsl r6, r7
bic r6, #0x0080
lsrs r7, #1
orrcs r6, #0x0080
orr r6, r6, r7, lsl #12
orr r6, #0x4000
b 2f
1: add r7, r3
ldrh ip, [r7, #2]
and ip, 0x8f00
orr ip, r6 @ mask in offset bits 31-24
strh ip, [r7, #2]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
bcc 1b
bx lr
#else
b 2f
1: ldr ip, [r7, r3]
bic ip, ip, #0x000000ff
orr ip, ip, r6 @ mask in offset bits 31-24
str ip, [r7, r3]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
bcc 1b
mov pc, lr
#endif
ENDPROC(__fixup_a_pv_ta
ble)
ENTRY(fixup_pv_ta
ble)
stmfd sp!, {r4 - r7, lr}
ldr r2, 2f @ get address of __pv_phys_offset
mov r3, #0 @ no offset
mov r4, r0 @ r0 = ta
ble start
add r5, r0, r1 @ r1 = ta
ble size
ldr r6, [r2, #4] @ get __pv_offset
bl __fixup_a_pv_ta
ble
ldmfd sp!, {r4 - r7, pc}
ENDPROC(fixup_pv_ta
ble)
.align
2: .l
ong __pv_phys_offset
.data
.glo
bl __pv_phys_offset
.type __pv_phys_offset, %object
__pv_phys_offset:
.l
ong 0
.size __pv_phys_offset, . - __pv_phys_offset
__pv_offset:
.l
ong 0
#endif
#include "head-comm
on.S"
解释以上代码
本文深入探讨了ARM处理器的缓存控制机制，详细解析了cache_on函数如何根据不同的处理器ID调用相应的缓存开启、关闭及刷新函数。通过分析处理器特性寄存器和缓存类型表，展示了如何匹配处理器ID并执行对应的缓存操作。
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